http://defect.opensolaris.org/bz/show_bug.cgi?id=6057
Aubrey.Li <aubrey.li at intel.com> changed:
What |Removed |Added
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CC| |aubrey.li at intel.com
--- Comment #1 from Aubrey.Li <aubrey.li at intel.com> 2009-01-11 00:51:58 ---
(In reply to comment #0)
> What I don't understand is why these P-state transitions are happening at all
> during the moderate loads...since we should only request a P-state transition
> if all the CPUs in the P-state domain become idle or when the first CPU on an
> idle domain becomes busy. Intuitively, that should be fairly
> rare...particularly above 50% utilization.
The problem is, event mode is using a per-cpu flag to lessen the transient
threads impact of state changes, but the transient domain utilization is
ignored.
Especially load balance policy could dispatch the thread to a different CPU.
This
doesn't change the domain utilization, but cause CPU0's utilization from 1 to 0
and CPU1's utilization from 0 to 1. Although the per-cpu utilization has
already been lessened, from the domain point of view, when switch to CPU0, it
will cause pstate demotion and when switch to CPU1, it will cause pstate
promotion.
These two pstate transitions are not expected because the domain utilization
doesn't change.
Does this make sense?
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