Vinay Devadas wrote: >> TM1/TM2 are automatic thermal protection mechanism, >> the result may be reasonable if they are enabled. Check them. > > Yes, I checked the IA32_MISC_ENABLE MSR and bit 3 was set. >
That's interesting. if you disable the p-state and turbo, would you see any APERF/MPERF difference between the system in light workload and the system in heavy workload? Thanks, -Aubrey > > ----- Original Message ----- > From: "Li, Aubrey" <aubrey.li at intel.com> > Date: Thursday, July 24, 2008 10:31 am > Subject: RE: [tesla-dev] Experiment Results on APERF/MPERF > registers - Need Clarification > To: Mark Haywood <Mark.Haywood at Sun.COM>, Vinay Devadas > <Vinay.Devadas at Sun.COM> Cc: tesla-dev at opensolaris.org > > >> Mark Haywood wrote: >> >>> Vinay Devadas wrote: >>>>> And never executed halt, right? >>>>> >>>> >>>> No, I just made the sampling thread sleep for the "interval >>> length". I did not halt the CPU. >>>> >>> >>> Sorry. I don't think it is supposed to matter anyway. If I read the >>> System Programmer's Guide description of APERF/MPERF correctly, >>> these counters only increment when in the C0 state anyway. So, OK, >>> I give up. If we are in P0 for the entire interval, then why isn't >>> APERF/MPERF equal to 1. Aubrey, do you have any ideas? >>> >> MPERF counter runs at the Max Non-Turbo frequency when the core is >> in C0. APERF, actual performance frequency clock count when the core >> is in C0, it will be impacted by TM1/TM2. >> >> TM1/TM2 are automatic thermal protection mechanism, >> the result may be reasonable if they are enabled. Check them. >> >> Thanks, >> -Aubrey
