Just some thoughts, and I hope I'm awake enough to type this... There seem to be several issues here.
In the "Figure 1" case "core" packet timestamps come from the kernel and the new packet timestamp will be added by the hardware engine. I understand the following question is outside the scope of this document, but how can one determine how well sync'd the internal clock is with the clock in the accurate timestamp engine? If we have TX and RX hardware timestamping capabilities, we can use NTP's interleave mode to communicate these timestamps as well. Having said that, I'm sure there is something to be learned from implementing Tal's proposal. H _______________________________________________ TICTOC mailing list [email protected] https://www.ietf.org/mailman/listinfo/tictoc
