Hi Magnus,

So I guess the verdict is that it is best to band limit your clock signal
with a low-pass filter. This filter is then still supposed to still allow
the necessary rise time for adequate PSSR. Doesn't PCB track impedance do
this type of band limiting for you? Or do you suggest adding a separate
RC-stage of some kind? The reflections due to impedance mismatch still
steers me away from this option.

Regards,

Stephan Sandenbergh   


Message: 6
Date: Wed, 28 Jun 2006 14:59:41 +0200 (CEST)
From: Magnus Danielson <[EMAIL PROTECTED]>
Subject: Re: [time-nuts] Conditioning clock signal paths
To: [email protected], [EMAIL PROTECTED]
Message-ID: <[EMAIL PROTECTED]>
Content-Type: Text/Plain; charset=us-ascii

From: "Poul-Henning Kamp" <[EMAIL PROTECTED]>
Subject: Re: [time-nuts] Conditioning clock signal paths
Date: Wed, 28 Jun 2006 12:37:29 +0000
Message-ID: <[EMAIL PROTECTED]>

> In message <[EMAIL PROTECTED]>, "Stephan Sandenbergh"
writ
> es:
> 
> >Now for the paradox: Do you filter your digital signal to lower the noise
> >bandwidth? Or do you want a high as possible rise time (slew rate) to get
> >the best PSSR?
> 
> The advantage to digital signals (ie: square-oid signals) as opposed
> to analog signals (ie: sines) is that the slew-rate is higher.  That
> means that it is less important at which precise voltage the
> L->H or H->L transistion happens and therefore you don't need
> precise analog reference voltages in your logic circuits.
> 
> The low slewrate of a sine would mean that even small changes
> in threshold voltage would come out as large jitters in time.

Worse yet, the broadband noise will make sure to add jitter. There is a very
direct relationship between slew-rate, noise and jitter. This jitter will
limit
the time-resolution of the measurement. Slew-rate is in a very direct
relation to amplitude and frequency. Slow changes in offset (due to power
and
temperature) will certainly contribute to wander effects.

Cheers,
Magnus



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