From: [EMAIL PROTECTED] Subject: Re: [time-nuts] Some results of PRS10 and Trimble Resolution Date: Wed, 28 Jun 2006 16:19:04 EDT Message-ID: <[EMAIL PROTECTED]>
Hi Said, > Using an interpolator with a slow basic clock as Magnus suggests is probably > the easiest way to prevent EMI issues, but it has some disadvantages such as: > > * You need to design a fairly tricky high-linearity charge pump to make it > work well, using high-quality components such as Polyester caps, low > INL/DNL/Tempco ADC's and ADC reference, or high quality comparators and > sample-and-holds, etc to make it insensitive to temperature changes etc. > This is > essentially an analog design, with voltages being captured by an ADC, then > converted to > time steps in software. > > * The interpolator needs to be calibrated to give good results, especially > if the charge pump is not very linear. This is also needed due to temp > changes, as well as the ADC's errors such as the INL/DNL etc. This could be > done > automatically, but does require a bit of circuitry and know how. You run into more of these problems if you go for larger gains. If you go for a modest gain of 10-200 you have still a fairly easy design-effort and besides, running a clock around 100 MHz isn't as large problem as it used to be. With a x100 scaling the 10 ns resolution has become 100 ps. For such a interpolator you can get fairly good result just by feeding it a short-pulse/long-pulse training (1 or 2 cycles - i.e. 10 ns and 20 ns). You can then use that for either compensation or better yeat - trimming of the currents. The larger gain, the more important the linearity becomes. You can either fight it by increase linearity or you can fight it by trimming up the scale and linearize it through a look-up-table. This however requires a method to produce various forms of time intervals with known occurence, but it has been done. > The advantage of the interpolator is that it can have a very high resolution > (ps) if designed properly. I have a Wavecrest interpolator board at home > that has 10ps resolution, and it is bigger than one of the old full-size AT > IBM > motherboards... its tricky circuitry to design and make it work well. One > interesting fact is that Wavecrest uses actual rigid coax cables wound up in > loops to create delays on that board! They do suggest to calibrate the system > > every 24 hours, or if there is a 5 Deg C change in temp. As we push digital up in clock, the timing resolution which used to be alot of black magic is becoming much more available. Look at the HP5335A, it used 10 MHz and a fairly simple interpolator design. Using the same basic design but running at 100 MHz (which comes cheap today) should give you 100 ps without too much of a head-ache. Infact, in the HP5335A they lost some precission in the way they treated data, so they only said 1 ns when they infact measured with 500 ps resolution. > Using the digital approach, you only need two parts: a fast PLD/FPGA, and an > external clock source (10MHz for example if the PLD has a PLL). Actually, today you use FPGA and interpolators together. You can infact get 100 ps single-shot resolution straight out of a FPGA, but you will have to spend some time on the EMI issues. > Depending on the PLD, you could get one that has an internal PLL running at > 500MHz or even faster from your external 10MHz. These fast signals are only > inside the FPLD/FPGA, so it's easy to shield the circuit to prevent EMI. You still need to care about propper decoupling caps. Some (actually a certain) FPGA manufactuers don't have a real PLL, but have relied solely on DLLs, but those are not as timing-clean as a real PLL can give you, so the internal jitter can actually be quite high. Cheers, Magnus _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
