From: "Stephan Sandenbergh" <[EMAIL PROTECTED]> Subject: Re: [time-nuts] Linear Interpolator Date: Fri, 30 Jun 2006 14:02:11 +0200 Message-ID: <[EMAIL PROTECTED]>
> Hi Ulrich, Stephan, > Thanks for the tip. And, also many thanks to Magnus for introducing me to > the concept of Time-to-Digital conversion. It is a brilliant and yet so > simple technique. (Until yesterday, I blissfully believed that a fast > clocking counter was one's best bet.) Indeed. Once you understood the basic concept, the particular interpolating technique you choose may vary as you see fit. > I also read the article posted earlier by Tom van Baak (Thanks Tom! This is > indeed a very comprehensive article.) It turns out that you can implement a > very elegant linear interpolator using a digital delay line inside a FPGA. > It is called the Vernier technique. From the article I understand that > resolutions of between 10s and 100s of picoseconds have been achieved for > various designs. > > Has anyone else used this Vernier technique with delay lines? I seems pretty > neat to me. It's what makes the HP5371A/HP5372A tick, it cranks out 200 ps resolution that way and keep counters at a mear 500 MHz. The HP5370A use a dual oscillator Vernier trick instead. It can be a bit of a challenge to get the FPGA to perform reliably thought. You could do a similar thing with a single delay-line but dual clocks of near same frequency. That might be a bit more reliable than the dual delay-line technique. > It means my hardware doesn't need to change. A software update will do the > trick :) Hehe... ;O) Cheers, Magnus _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
