Hi fellow time-nuts, Stephan Sandenbergh wrote:
> I also read the article posted earlier by Tom van Baak (Thanks Tom! This is > indeed a very comprehensive article.) It turns out that you can implement a > very elegant linear interpolator using a digital delay line inside a FPGA. > It is called the Vernier technique. From the article I understand that > resolutions of between 10s and 100s of picoseconds have been achieved for > various designs. > Has anyone else used this Vernier technique with delay lines? I seems pretty > neat to me. I'll take this opportunity to plug something I wrote for last year's UKW-Tagung (VHF-conference) in Weinheim: "Increasing the resolution of reciprocal counters" which shows how to use the Digital Clock Management feature of the Spartan series of FPGA to achieve a 16-fold increase in resolution, resulting in a 625ps resolution (1.6GHz reference) at the moment. This technique indeed uses a similar kind of delay-line, but integrated in the DCM which provides calibration and phase-shifting. http://a48046.upc-a.chello.nl/~paul/Reciproke.pdf Regards, Paul Boven. _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
