Hal Murray wrote: Suitable TDC chips are available from [1]http://www.acam.de/ [2]<http:// www.acam.de/> In particular the TDC-GP1 has a resolution of better than 250picosec with a range of 200 millisec, which should be more than adequate for measuring the time delay between GPS and local standard derived PPS pulses.
Although these chips are a little pricey at around the 100 euro mark they are a lot cheaper than an Agilent/HP 53131 or its equivalent. Has anybody tried kludging something together without using expensive parts? I'm guessing that the general idea is something like an R/C feeding an ADC. Hold the R/C reset until time1, then let it start charging up. At time2, shut the door on a sample/hold that's probably built into the front end of an ADC. Then wait until things calm down and read the ADC. If I start with a 10 MHz clock, that's 100 ns. An 8 bit ADC gives a span of 2.5 clocks for a resolution of 1 ns. Lots of handwaving here. A 1 ns resolution needs an ADC or S/H with an input bandwidth in the ballpark of a GHz. My quick scan for a cheap/fast ADC didn't find anything interesting. So this is probably a wild goose chase. I wonder if it is reasonable to calibrate a slower ADC. The input signal will be stable. Digikey has the TI TLC5540 at under $6. It says 75 MHz input bandwidth but 30 ps aperature jitter. (That's just the first one I looked at. There are probably better ones.) Suitable sample and holds are a little hard to come by these days. One traditional method of building a time to amplitude converter (TAC) is to use a bipolar transistor longtailed pair to charge an intially discharged capacitor for the duration of the short time to be measured/interpolated. An ADC then samples the capacitor voltage which is proportional to the capacitor charging time. With a modern capacitive charge redistribution ADC like the AD7450 there is no need for a buffer amplifier as the ADC input appears like a capacitor during the sampling phase. It is necessary is to allow the ADC input to settle after the longtailed pair is switched off, before beginning the ADC conversion cycle. Once the ADC conversion is complete the capacitor can be discharged by turning on a shunt small signal MOSFET. A long tailed pair using a pair of small signal RF transistors will switch the output current from one collector to the other in less than a nanosecond if suitably high cutoff frequency fast low capacitance transistors are transistors are used The collector current is at most a few hundred pA (at room temperature)when the transistor is turned off. A resolution of a around 250 picoseconds is possible with an interpolator range of 1microsec when a 12 bit ADC like the AD7450 is used. The long tailed pair switching time is limited by the emitter to emitter inductance when discrete transistors are used, an integrated pair with the emitters connected together on chip will switch faster than a discrete pair. The ADC need not have a particularly low jitter or fast acquisition time as the capacitor voltage is stable when sampling is complete. It is essential to use a low dielectric absorption capacitor such as a ceramic capacitor with a C0G/NP0 dielectric, although the low duty cycle in this application when making 1-2 measurements per second relaxes this requirement somewhat. Another traditional time interval interpolation technique is the Wilkinson technique where instead of sampling the capacitor voltage, the capacitor is discharged by a curreent say 1/1000 of the charge current, a comparator monitors the capacitor voltage an a counter measures the time for which the capacitor voltage is non zero. The conversion gain is only dependent on the ratio of the two current sources with a 10mA charge current and a 1uA discharge current a timing resolution of 10 picosec can be achieved with a 10MHz rundown clock. A fast low input bias current comparator with a latched output should be used to preserve the sensitivity and linearity of the conversion. The comparator is lached on for most of the rundown clock period and its input polarity is sampled only for a short time on say the falling edge of the rundown clock. The comparator output state is sampled half a rundown clock cycle later by a following D flipflop. This technique precludes the possibility of comparator oscillation due to input outpuut feedback (it only takes a fraction of a pF of stray capacitance to cause this with a high speed comparator). Using hysteresis, whilst avoiding oscillation, decreases the resolution of the comparator. A comparator resolution of less than 100uV is readily achieved with a suitable comparator. The output of the D flip flop is used to gate the interpolation counter. Alternatively the flipflop transitions can be used to sample a continuously running counter. At the end of the conversion cycle a MOSFET discharges the capacitor. This technique can take a millisecond or more to complete the rundown cycle. However this isn't an issue when making 1 measurement a second. To avoid the problem (at least with discrete components) of rapidly switching on the 1uA rundown current source it can on all the time, producing a stable initial capacitor voltage of a few tens of microvolts With a traditional time interval counter 2 interpolators are required one for the stop channel and one for the start channel. If a free running counter is clocked by the reference frequency then it can be sampled by the output of a PPS synchroniser and a single interpolation circuit is required to measure the input to output delay of the synchroniser. The resultant sequence of time stamps can be analysed to derive the equivalent time interval counter measurements. Another possibility is to just use a large resistor connected to a stable voltage to discharge the capacitor, this avoids the difficulty of building a suitable 1uA current source using discrete components. The charge-discharge is non linear but this is easily measured and/or calculated from the known component values. The nonlinearity can then easily be corrected by a microprocessor. It is also possible to use a pair of opamps configured as a high gain integrator whose feedback capacitance is ramped up and down. Resistors can then be used to define the runup and rundown currents with series/shunt small signal mosfets connected to the integrator summing junction to steer the currents either into the summing junction or to ground. Again the discharge current source (resistor) can be connected directly to the summing junction and a small signal MOSFET is used to discharge the integrator feedback capacitor. With the correct topology a pair of relatively slow opamps (<50 MHz) can be used with high accuracy. 1/3 of a 74HC4053 can be used to implement the series shunt current steering switch. References 1. http://www.acam.de/ 2. http://www.acam.de/ _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
