Dr Bruce Griffiths wrote: > The design is probably a pair of low noise n channel JFETs > configured as a push push doubler. > Inputs driven in antiphase so that each FET conducts ffor > opposite 1/2 cycles with the 2 FET drains connected in parallel. > A bypassed trimpot connected between the FET sources being > used to compensate for FET mismatch. > The low frequency design probably uses a common source design > whilst the VHF version employs a pair of common gate devices. > An RF transformer connected between the the common drain and > the positive is used to drive the load.
OK, so I feed the input (of suitable gain) to a trifilar (or bifilar with tap) wound toroid to get the phase and antiphase. And the rest is just a pair of standard JFET RF amplifiers. I.e., I should use standard JFET RF amplifier biasing techniques, either employ a long tail or, alternatively, measure the pinch-offs and Idss's and pick my source resistors appropriately. If I'm getting all this right, the circuit looks something like the attached. Yes? Thanks for the input. -ch
doubler-concept.pdf
Description: Adobe PDF document
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