> If you mean multiply the 15MHz output by 2/3 to generate 10MHz, simply > use asynchronous divide by 3 counter (2 fliplops) to produce a 5MHz 1/ > 3 duty cycle (or 2/3) output then filter out the 10MHz 2nd harmonic > component with a bandpass filter. The 3rd Harmonic (15MHz) will > conveniently be very close to a null (only departure from exact 1/3 > duty cycle and clock feedthrough from the divider prevent a perfect > null).
There is another approach that works to multiply by 2: Use the other edge of the clock. I think I saw this in an app-note from Xilinx. The idea is to use an XOR gate and delay to make a pulse on each clock edge. If you include a FF as part of that delay then you have a reasonable guarantee that the clock pulse will be wide enough to clock a (similar) FF. This only works for slow clocks, but 30 MHz is quite slow for modern logic, at least once you get inside the chip. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
