[EMAIL PROTECTED] wrote: > > In a message dated 2/23/2007 05:58:09 W. Europe Standard Time, > [EMAIL PROTECTED] writes: > > Current mode ramp generators using long tailed pairs to switch the > charging current for a capacitor are the time honoured approach for fast > ramp generators. > > > Hi Bruce, > > would you have some sample schematics for a more modern, faster version of > this than let's say the one used in the 5334A etc that you could share? > > thanks, > Said > <BR><BR><BR>**************************************<BR> AOL now offers free > email to everyone. Find out more about what's free from AOL at > http://www.aol.com. > _______________________________________________ > time-nuts mailing list > [email protected] > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > > Said
The following paper illustrates one way of building such an interpolator using a custom IC. http://www.imec.be/esscirc/papers-96/122.pdf The critical part which limits switching speed in a discrete limitation is the inductance of the connection between the two emitters of the long tailed pair switches. It would pay to use a transistor array (e.g. HFA3046 or even better a faster version of the CA3054 or CA3102) where the emitters are already connected together on chip. With a modern capacitive charge redistribution ADC, the ADC sampling capacitance could form part of the capacitor being charged by the current source. The current source is gated on for the time interval to be measured, the ADC conversion is then triggered after waiting long enough for the charge on its sampling capacitance to settle. Following the conversion the ramp capacitor is discharged. The capacitor reset switch being opened just before the current source is turned on. The required timing is easily generated by a 3 (or more) stage synchroniser. The interpolator being used to measure the input Its actually much easier to use a TDC chip which can achieve a resolution of 10ps and a differential nonlinearity of a few picosec as long as the delay measured by the TDC is greater than 200ns. Lower frequency synchroniser clocks (5-10 MHz) suffice compared to those required with a ramp type interpolator of the same resolution. Essentially a pair of TDCs is used to measure the delay of the start and stop channel synchronisers, with a 3 stage synchroniser the measured delays by the TDCs can easily be kept in the range of 200-400ns even though the time interval between the start and stop edges may be a short as a few tens of picosec. Bruce _______________________________________________ time-nuts mailing list [email protected] https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
