Dr Bruce Griffiths wrote:
Lars Karlsson wrote:
Bruce-
There is a minor problem in the schematic. A capacitor have to be added
between R103 and R104. This will prevent the bias on pin 3 from
being shorted to the ground via R101 and R102. Also, C103 is not
required
as long as the diodes stays connected to R103.
Lars
PS
Interesting to see the "revised phase comparator" I will implement
it into a CPLD to find out what the maximum speed will be.
Lars
Oops!
R101 and R102 should have been on the other side of the capacitors (C101
+ C102) as in the revised schematic attached.
This is the way its done in the K34-5991. It looks a little strange but
works well (Both for HP and even when simulated using the transient
analysis option in pSpice).
The 50 ohm termination was an option in the K34-5991, R101 and R102 have
a fairly high (1W each) dissipation with 10V rms input.
Dissipation in R103 is also fairly high at 220mW or so with a 10V rms
input.
If a minicircuits RF transformer were used at the input, the input
voltage would be limited to about 3.5Vrms and the lower frequency limit
to about 100KHz or so.
To match the input specifications as the K34-5991 the HP style input is
required.
NB when implemented in a CPLD, I would use the Q output of U101A as a
synchronous enable for U103A, U103B U105A U105B U104B and U106B and
clock these directly from CLKB. I didn't do in the 74CX version as
suitable devices aren't readily available and adding extra gates to the
JK inputs of a JK flipflop would add complexity and slow the circuit
down. In a CPLD this method only requires 2 clock inputs (CLKA and CLKB)
and all the required gate resources are built in.
One possible option if the power supply current can be kept down, is to
power the circuit from batteries.
Bruce
_______________________________________________
time-nuts mailing list
[email protected]
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
