I`ve been puzzling over the reasons why one synthesised signal generator
produces more close-in noise than another,
and thought that one of the reasons for this noise would be jitter on the
digital signals applied to the phase detector producing FM sidebands from the
VCO. What then are the causes of jitter in digital circuits? A poorly regulated
PSU to the logic might cause the hi/lo decision Voltage to vary, and this,
combined with finite rise, and fall times, could cause jitter, but what are the
things a designer can do to keep jitter to a minimum? Could the group comment
please.
...............................................................................Don
C.
PS : I apologise if this question is a bit off topic, but minimising jitter is
also important to precise time and frequency measurement [as is reducing
close-in VCO sideband noise].
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