thanks for the positive feedback, In xilinx fpgas, for example, the recovery time after a metastability issue is quite fast as reported in this paper
http://www.xilinx.com/support/documentation/application_notes/xapp094.pdf The capture window of metastable state is 0.01fm (page 2). Probably this window is moving around a bit, but this 0.01fm sounds promising. In page 3 "When granted 2 ns of extra settling delay, the problems caused by metastability are almost eliminated, as their MTBF exceeds millions of years." So we can just solve the glitch problem by adding a shift register as Bruce suggested. I think the major concern may be crosstalk, but using lvds or ecl logic and placing the IOs far away one from each other may help to reduce it a bit. Now a DMTD architecture can be almost completely based on a FPGA where some LVDS IOs would contain the D flip-flop mixers, with their clock input connected to the reference frequency and the D input to the clocks under test. The FPGA would contain a 32 bit free running counter clocked by the reference clock. Every time I detect a transition on my LVDS IOs the free running counter is latched and passed to a FIFO. Then the work can be passed to a data analysis program (of course through an LVDS serial link) to do all sort of funny calculations. I wonder how good this system could eventually be if we reduce crosstalk to a minimum. Pablo On Wed, Dec 3, 2008 at 9:01 PM, Bruce Griffiths <[EMAIL PROTECTED]> wrote: > Lux, James P wrote: >>>> Cheers >>>> >>>> Pablo >>>> >>>> >>>> >>> Pablo >>> >>> Flipflop mixers tend to produce glitches at the beat >>> frequency transitions. >>> A digital PFD in a PLL doesnt produce a beat frequency output >>> when locked so such glitches arent a problem, >>> >>> >> >> I don't know that this is the case with modern PLL PFDs.. If only because >> glitches at the transitions would cause other problems, so there's an >> incentive to get rid of them. >> >> >> Jim >> >> > Surely metastability may occur when the mixer flipflop D input > transitions occur close to its active clock transitions? > > There is at least one patent (US5053651) that claims to eliminate such > glitches in a digital mixer, however its output beat frequency is half > the difference between the input frequencies. > > Bruce > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
