Joe Joe Gwinn wrote: > Bruce, > > At 9:50 PM +0000 12/19/08, [email protected] wrote: > >> Message: 7 >> Date: Sat, 20 Dec 2008 10:38:26 +1300 >> From: Bruce Griffiths <[email protected]> >> Subject: Re: [time-nuts] Sub Pico Second Phase logger >> To: Discussion of precise time and frequency measurement >> <[email protected]> >> >> Joe >> >> Joe Gwinn wrote: >> >>> Bruce, >>> >>> At 3:54 AM +0000 12/19/08, [email protected] wrote: >>> >>> >>>> Message: 5 >>>> Date: Fri, 19 Dec 2008 16:51:55 +1300 >>>> From: Bruce Griffiths <[email protected]> >>>> Subject: Re: [time-nuts] Sub Pico Second Phase logger >>>> To: Discussion of precise time and frequency measurement >>>> <[email protected]> >>>> >>>> Joe >>>> >>>> Joe Gwinn wrote: >>>> >>>> >>>>> At 11:48 PM +0000 12/18/08, [email protected] wrote: >>>>> >> >>> >> [snip] >> >> >>> >>> >>>> Some claim to be able to sync to an SPDIF input but the resultant jitter >>>> may be large. >>>> >>>> >>> Why large jitter? Bad implementation? >>> >>> >>> >>> >> I'm just suspicious, although I did see some data somewhere that seemed >> to confirm my suspicions. >> The S/PDIF signal has to be a valid SPDIF signal not just a square or >> sine wave clock. >> Output sample rates (for the AP192) are then identical to that of the >> the S/PDIF source which is limited to >> 192, 176.4, 96,88.2 48, 44.1 32 KSPS. >> > > I did a little looking. I bet that the sync quite well, but this > signal is pretty complex. One assumes that there is a box that takes > in a 10 MHz ref and does the rest, because the broadcast industry > does use atomic clocks. > > > Ulrich has built a circuit that takes a sampling frequency input derived from a 10MHz GPSDO output and produces an S/PDIF output for this application. Its certainly worth trying since all the specs for the sound card aren't readily available. >> > >> >> >> >> A few divide and mix stages will be required to achieve >> a spur free resolution of 10Hz. >> >>>>>> >> >>>>>>> That is a traditional approach. But are there alternate >>>>>>> approaches that >>>>>>> >> >>>>> have now become practical? >> >>>>> >> >>>> Diophantine frequency synthesis? >> >>>> >> >>>>> From the sound of the name I think so, at least in the last DDS >>>>> stage, as done by that patent. >>>>> >>>>> >> >>> But I was fishing. >> >>> >> >>>> Conventional Diophantine synthesis uses number theory together with 2 or >>>> 3 conventional synthesiser loops to achieve very fine resolution whilst >>>> >> >> maintaining a high PLL phase detector input frequency. >> > >> >>> In a sense, the concatenated DDS approach is a divide-and-mix chain. >>> >> > Perhaps there is a parallel here. >> > >> The DDS based equivalent (of the dual PLL Diophantine synthesiser) would >> use a pair of DDS chips each replacing a conventional PLL in the >> Diophantine frequency synthesiser, the output frequency of each having >> zero phase truncation spurs. >> >> Both DDS clock sources should be spur free and have a frequency ratio >> that is a selected fixed rational fraction. >> > > A M/N PLL chip can arrange this. I recall that Silicon Labs makes > such a chip, which requires a parameter load on power-up, so a > computer or FPGA is needed. > > > M and N only have to be relatively prime (ie the GCD of M and N is 1). The ratio of M/N should also be close to 1. If the spacing of the phase truncation spur free output frequencies is about 10kHz (for either DDS) and M, N ~ 1000 the resultant mixer output frequencies would have a spacing of about 10Hz which may be adequate for this application.
>> A conventional mixer would then be used to either add or subtract the >> two DDS output frequencies. >> If the ratio of the 2 DDS clock source frequencies is appropriately >> chosen the spacing between the resultant mixer output frequencies can be >> much finer than the spacing between the truncation spur free outputs of >> either DDS chip. >> The DDS and mixer outputs should be filtered to remove harmonics and >> other unwanted frequencies. >> > > If the DDS chips are well chosen, we will get sin and cos outputs, > and so can implement a dual-mixer phasing scheme to yield only the > sum frequency or only the difference frequency, greatly reducing the > amount of filtering needed. The better balanced the channels are the > better the cancellation of the unwanted term. This is basically the > phasing method of single-sideband signal generation. > > > >> One drawback is that selecting the output frequencies of the 2 DDS chips >> required to produce the desired output frequency is somewhat complex. >> Since one almost certainly needs a computer of some sort to set the DDS >> frequencies this shouldn't be a significant issue. >> > > Yes. Basically, every digital chip in this scheme requires a > computer of some kind. What I've seen used is a small CPLD to do the > initial parameter loads, and then to run the show. > > Joe > > Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
