> If the plan is to drive a mechanical clock, I assume long term stability is > more important than phase noise. Many small microcontrollers (I use 8051's > from Silabs) have a built-in PLL that can be set to run at 15 MHz from an > external 10 MHz reference (applied to the external oscillator input), and > use the program space to implement a divider that will give you exactly 60 > Hz. That is a one chip solution. The processor will accept the sinewave from > the reference oscillator without extra shaping circuit.
In case your favorite chip doesn't have a PLL... You can run directly from a 10 MHz clock as long as you can tolerate a bit more phase noise and/or spurs. The software just gets a bit more complicated. Instead of dividing by N, it has to mix delays of N and N+1 in the right ratio. You can also do it with a DDS in a FPGA. The trick is to use a decimal adder rather than a binary adder. 60/10000000 in binary isn't a clean fraction so the clock will drift slightly. [This should be simple, but I'm not sure I've got it right.] On the other hand, if you use a 64 bit binary adder, that's 16*2^30*2^30 or 16*1E9*1E9 or 16E18. Call it 1E19. We are clocking at 10E7 Hz, so (worst case) the counter will be off by a full cycle every 1E12 seconds. There are 3E9 seconds per century. So after a century, the clock would be off by 3E-3 cycles or 50 microseconds. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.