Fantastic job on reverse engineering the counter and then actually doing
something to modernize it. I might guess implementing this on one of the
counters out of 3 would be both educational and interesting. Ending up with
a modern on the network counter.

Took a look at your setup and bench. So the support for the 5370 is a HP
vector network analyzer. Now thats some support. :-) I might tend to have
the two flipped in the stack.
So you are suggesting the potential to make this operational to a wider
audience. Any thoughts on a timeline? I personally have no problems
soldering in 40-60 wires from a daughter board as an example.

On Sun, Jul 24, 2011 at 8:12 AM, Bruce Griffiths <
> wrote:

> Poul-Henning Kamp wrote:
>> In 
>> message<77E0FBA5-AA78-4399-**<>>,
>> John Seamons writes:
>> I would worry a bit about the PLL locking too, but I have no idea how
>> to actually measure it.
>> I think the 1sec max gate-time is related to the eventcounter width,
>> but it might be possible to simulate a wider counter in software.
>> The obvious idea for advanced functionality is calculation of
>> allan deviations
> The PLL sample frequency is around 0.8MHz so that trigger rates approaching
> this will alter the PLL loop parameters.
> Trigger rates greater than the PLL sample frequency (200/256MHz) will
> likely cause lock to be lost.
> The 5359 (uses the same vernier oscillator assembly) overcomes this by
> using a digital sample and hold  to set the VCO control voltage.
> However periodic auto calibration by closing the loop is required to avoid
> drift.
> Bruce
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