[email protected] said:
> I'm curious how a 10 MHz-driven high-end DDS would generate 32 kHz with the
> lowest possible jitter?
What do you mean by high-end DDS? A chip from Analog Devices or one from
Xilinx? :)
If you use a classic DDS chip with a binary adder and ROM, it will have low
jitter but the frequency will be off a tiny bit. My calculations...
24 bits:
54975 => 32767.653465
54976 => 32768.249511
32 bits:
14073748 => 32767.998054
14073749 => 32768.000382
If you use a FPGA, it's something like this:
X = X + 32768
If X >= 10000000
output clock pulse
X = X - 10000000
You get the subtract for free if you are using decimal arithmetic and ignore
the overflow. You can do it with binary addition if you pipeline things
right and put a mux in front of the adder. It either adds 32K or adds
(32K-10M).
That makes a 1 clock wide clock pulse, 100 ns at 10 MHz. If you want a
square clock, make a 2X clock and toggle a FF to divide by 2.
It will have the right long term frequency, or at least as good as the input
clock.
It will have lots of jitter. It's not Gaussian type jitter but spurs.
Peak-to-peak will be roughly one clock period.
------
I don't know how to compute the jitter on traditional (binary, ROM) DDS
chips. Peak to peak will also be roughly one clock period in the raw output,
but the output is close to a sine wave so some filtering would easily reduce
the jitter.
I'm pretty sure they have spurs and that they are smaller and farther out if
the ROM is wider and deeper.
Both DDS chips and FPGAs usually contain a PLL/DLL to get a faster internal
clock rate. That would reduce jitter.
I don't know enough matlab to be able to simulate this. Another time sink when
I get the time.
--
These are my opinions, not necessarily my employer's. I hate spam.
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