> Date: Fri, 7 Dec 2012 22:28:20 -0500 > From: Bob Camp <lists at rtty.us> > > Hi > > A lot depends on exactly what the interrupt structure is. It may also depend > on the phase of the cpu clock relative to the pps signal. What's reasonably > sure is that there is indeed some offset between the two where the answer is > indeed "ft's" random. Another thing to check - how wide is the random region? > > Bob > > On Dec 7, 2012, at 9:19 PM, Chris Albertson <albertson.chris at gmail.com> > wrote: > >> One more test to try. Connect one PPS signal to both GPIO ports and see >> how close to zero offset you get. It would likely be random which gets >> read first. >>
I'm using an Atheros ar71xx platform, the GPIO driver does not use interrupts so I'm using an experimental polling PPS driver: http://code.google.com/p/openwrt-stratum1/wiki/PpsGpioPollDriver The jitter is low, about 100 ns p-p (see graph on the main page). A "TIC mode" could be added to measure the difference between events on two GPIO ports. I had an NTP server which had PPS on the serial port DCD and the parallel port ACK, both derived from the same source. When both are connected, the serial port timestamps are 10 us late. When the parallel port is disconnected, the delay drops to 5 us. Probably the parallel port ISR is executed first and delays the serial port ISR. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
