Has anyone else looked at the Parallax Propeller processor for timing functions? It has 8 cooperative cores and has a number of intrinsic timing functions for measuring intervals accurately, or for generating tightly-timed repetitive pulse trains, within the frequency accuracy range of the processor's clock. (Up to 80MHz by spec but the chip runs at 100MHz just fine.) One can dedicate one or more cores to performing the low-level timing functions while using another core to handle housekeeping functions asynchronously. The only real limitation I have encountered is no built-in A:D or D:A. (Low-pass filtered PWM is how I handle D:A usually.) The processor is 32-bit throughout so one can do reasonable timing operations using integer arithmetic.
Using the Propeller to discipline an oscillator using 1pps would be trivial. Use the oscillator to be disciplined as the processor's clock and use the 1pps to gate an accumulator. (Use the internal PLL to multiply the reference oscillator up to 40 or 80 MHz to increase resolution in the accumulator.) This operation is performed with a single machine instruction. You just let one core sit there and process the error accumulation from the reference and the 1pps while another core processes the error and sets a third core generating the PWM error signal to correct the reference. Using multiple cores means that one really doesn't have to worry much about interrupt latency (just poll) or race conditions. -- Brian Lloyd, WB6RQN/J79BPL 706 Flightline Drive Spring Branch, TX 78070 [email protected] +1.916.877.5067 _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
