Hello John M., Thanks for the plot. Did you take that out past 1MHz - I assume it stayS 'flat' - maybe not.
What explains that little spike at 10kHz for the AD9511? Interesting artifact. Thanks, John W. On Thu, Feb 6, 2014 at 12:44 AM, John Miles <[email protected]> wrote: > (Different John here) Some quick and dirty residual PN measurements made > on > the 100EL family versus some newer clock distribution chips from Analog > Devices: > http://www.ke5fx.com/100EL_vs_AD.png > > These may not be directly applicable to 100LVEL parts and shouldn't be > taken > as gospel in any case, because real-world results are dependent on signal > levels and power supply contributions. But the overall trend of lower 1/f > noise than CMOS with similar broadband floors will probably hold for all of > the current-generation "fast ECL" parts. More data would be good to have. > > -- john, KE5FX > Miles Design LLC > > > Hello John, > > > > Did you happen to do any phase noise measurements? > > > > Thanks, > > John W. > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
