Bob Stewart wrote:
Tom tried to steer me to the PICTIC recently, and I sort of brushed him off, because, quite frankly I didn't understand. Now that I've really looked at it, it's a much better idea than using a dsPIC33 and brute-forcing it. But, I don't really need everything the PICTIC offers so I started doing surgery, and this is what I've come up with.
The nsVolts would feed one of the 10-bit ADC channels of the 18F2220 on the VE2ZAZ board, and the 1PPS signal does the obvious. I had no idea what to use for the RC, so I used smaller and smaller values till LTSpiceIV showed a large range over 360 degrees of phase. I realize that's probably a bad idea, but I have no point of reference, nor do I probably need the accuracy that would otherwise imply.
The 1PPS input passes through the enabled tri-state buffers U2A and U2C to
charge the cap until the Q output from the D-flop is sent high from the 10MHz
signal and disables U2C. When the 1PPS goes low, the cap is discharged and the
D-FLop is reset. In practice, the chips would be 74AC types. I could only
find LTSpiceIV models for 74HCT chips. LTSpice says it's workable, but in
practice, I don't know. It might be finicky or unstable. Any comments would
be welcome.
http://www.evoria.net/AE6RV/TIC/TIC.png
Bob - AE6RV
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You should also include the effect of the A/D converter sampling
capacitance and saampling switch series resistace in the model. Since
the RC time constant of the sampling switch and associated sampling
capacitor can be 1us or more (temparature and Vcc dependent) the voltage
waveform at the sampling capacitor differs significantly from that
predicted by your simple modeel.
Aside from the nonlinearity due to the non constant charging current the
principle limitation on the resolution is due to the variable interrupt
latency for ADCs where the conversion is triggered by software.
This problem can be avoided if the ADC conversion can be triggered
directly by an external signal.
Bruce
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