Attila wrote:
Having put the circuit through Spice, I see that the current through
the tail fluctates violently during the time when the current switches
from one transistor of the pair to the other. The reason for this seems
to be that the f_t of the current source transistor is too low to compensate.
Trying to replace the current source with an RF transitor like BFU520
that has an f_t of 10GHz helps to dampen these fluctuations by a factor of 2,
but they are still there.
The transation frequency of the current source transistor is part of the
cause, but the primary cause is generally the capacitance of the CS
output node to ground. Some designers put an inductor in series with
the output, but I have never found this to be very effective [except in
poorly-designed simulations] due to the self-capacitance of the
inductor. Much better, IME, is to add a cascode device to the current
source. (See attached images.) This has the added benefit of
increasing the output resistance. This increase can be very substantial
(several orders of magnitude) if you use a FET cascode device as shown.
Why do people use general purpose transistors in these places, even
though RF transistors definitly improve switching behaviour?
I dimply remember that someone said/wrote once, that RF transistors have
a higher noise. But if I look at the datasheet, the quoted noise figure
for the BFU520 is <1.6dB while the noise figure of the 2N3904 is 2dB best case.
I, for one, have said this, but you are not remembering the whole point.
RF transistors are generally considerably noisier AT BASEBAND than GP
transistors, both because their geometries are inherently noisier and
because they have *much* higher flicker noise corner frequencies
(usually 10kHz to some MHz for RF transistors, compared to 10Hz-1kHz for
GP transistors). One might think that this would not matter at RF, but
the flicker noise modulates the bias of the transistor (and sometimes
other circuit elements), leading to both simple noise modulation as well
as phase modulation. RF transistors are not specified for noise at
baseband.
Referring to the attached images:
Circuit 1 (files ...01a and ...02a) is an LTspice simulation of a
cascoded ~3mA current source running into a node that shifts up and down
by 1v at 10MHz with rise and fall times of 1nS (vaguely simulating the
emitter node of a BJT differential pair switching at 10MHz). The green
trace is the current source output (drain of J1), the red trace is the
collector of Q1, and the cyan trace is the voltage forced at the CS
output through its internal 50 ohm resistance. Only the positive
transition is shown -- the negative transition is substantially the
same. The current increases by ~25% during the 1nS transitions due to
the output capacitance of the FET. NOTE: There will also be stray
capacitance at the output node, which will make this worse in practice.
Circuit 3 (files ...03a and ...03b) adds an actual differential pair
with unbalanced 2v p-p drive. As expected, the simulation shows
somewhat larger and somewhat longer perturbations at the transitions.
General comments:
Like any simulation, one needs to understand the limitations of both the
models used and the circuit choices made by the designer. I cannot
possibly write enough here to cover the particulars of this simulation
adequately. While my experience tells me that my choices are reasonable
and that the simulation is generally valid, there are still details to
be mindful of. You are warned!
I make no claim that these are the best devices to use for a 10MHz TAC,
although IME they are reasonable choices.
I modeled the ...01a circuit using a BFR90A BJT as the cascode device,
and the simulation showed that the current spikes were reduced by about
50%. However, my experience tells me that this would not hold in
practice. The simulation also showed that the DC output resistance fell
from nearly 300Mohm with the FET to only 1.4Mohm -- which experience
tells me is in the ballpark of how the real circuits would perform.
Best regards,
Charles
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