Good morning

I agree that 1deg is overkill but I was simply extrapolating one extra decade 
from BOB kb8tq's "backing off a bit" comment where he got down to 10deg. :-)

10MHz is an obvious sample rate - sorry, that fell into a blind spot here!

I think I will get distracted over Christmas sketching out some designs ...

Thanks - John

-----Original Message-----
From: Poul-Henning Kamp [mailto:[email protected]]
Sent: 4 December, 2018 11:03 PM
To: Discussion of precise time and frequency measurement 
<[email protected]>; John Moran, Scawby Design <[email protected]>
Subject: Re: [time-nuts] new WWVB BPSK dev board

--------
In message 
<am0pr03mb4129fbd0922805fc14b8cefde4...@am0pr03mb4129.eurprd03.prod.outlook.com<mailto:am0pr03mb4129fbd0922805fc14b8cefde4...@am0pr03mb4129.eurprd03.prod.outlook.com>>,
 "John Moran, Scawby Design"
 writes:

>However, fast A-Ds are not particularly cheap and you would need circa
>50MHz sample rate to resolve 1deg of the carrier, and TVB has already
>stated that there are no time benefits to BPSK, so this is all just an
>interesting technical exercise, isn't it?

I admit it would be interesting to do the allan variance on it, but measuring 
the carrier to 1 degree in every single cycle is waaaaay overkill.

1 MHz sampling rate is fine, but go for 5 or 10 MHz so you can drive the ADC 
directly from your house-standard.

And BPSK *does* improve the timing, because you can very precisely measure when 
the change of phase happens, and it since it happens at a carrier zero-crossing 
you can filter it down to +/- sample.

--
Poul-Henning Kamp       | UNIX since Zilog Zeus 3.20
[email protected]<mailto:[email protected]>         | TCP/IP since RFC 956
FreeBSD committer       | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

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