I have to draw your attention to practical aspects of why some designs use FLL rather than PLL.
Consider a GPS locked OCXO outputting GPS synced 10MHz signal. Properly designed control loop will not produce much (if any) difference when the reference (GPS signal) is present. In the end, integral of zero is zero. When reference (GPS lock) is lost the things are very similar too, holdover is just flying blind in the rough direction you were facing last. Accumulating frequency and phase offset on the way. However, when reference is restored the things are much different. After regaining the reference (which in case of GPS signal has unambiguous absolute time embedded into its phase) *proper* PLL loop will try to correct for slipped phase at the highest slew rate. This can be huge. If phase has drifted 1ms apart the loop will have to slew the phase all the way until it gets those 10,000 cycles out of the way. This usually looks ugly in frequency domain and is very disrupting if you are using the device as frequency reference rather than an absolute time reference. Proper FLL loop will just gently (and reasonably quickly) get your frequency back and forget about all the lost phase. Which is what a lot of users want. Initially, I have used PLL mode on GPS clocks that I am making, but switched over to FLL during the last few years. Cheers Leo _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
