Erik,
You also also test the issue by vary the slew-rate of the input signal.
The trigger circuit will convert voltage noise into time noise, and any
such leakage will become larger time for slower slew-rate.
You can look up Collins paper amongst others for zero-cross-detectors.
Combining that with the knowledge of leakage can be fruitful to
understand the analog side of it.
The cross-talk comes in two flavours, one is just straight
signal-leakage, typically capacitive coupling, the other is indirect
through common ground-bounce which is really inductive.
High resolution counters have been used to analyze signal integrity
issues like these. An alternative approach is TDR/TDT, which I tend to
fancy.
A good way to characterize an input is to measure the RMS for a sweep
over all phase relationships of the incomming phase and that of the
coarse clock. One need to make sure one covers those phase relationships
equally enough.
Cheers,
Magnus
On 2022-02-04 11:49, Erik Kaashoek wrote:
Magnus,
Thanks, good input. To check if there is "pulling" between the two
counter inputs I used two signals generated by two PLL's from the same
OCXO. First measurement is both at 10MHz. The ratio of these two
signals was measured in the two counters using a shared 10MHz
reference with a 0.1 s gate time. The ADEV behaves well and starts
below 1e-9.
When one of the signals is shifted with 0.1 Hz (ratio change 1e-8) or
0.2 Hz (ratio change 2e-8) the ADEV starts to show oscillations and
the frequency difference shows a pulling pattern that repeats every 10
s for 0.1 Hz difference and 5 s for 0.2 Hz difference.
Both ADEV and frequency difference plots are attached
The difference between the 10MHz from the signal generator and the
10MHz reference in the counters was large enough to not create any
visible pulling using a 0.1 s gate time but when I brought the 10MHz
from the signal generator close (within 0.2 Hz) to the 10MHz reference
in the counter the interaction became very visible and the repetition
rate nicely varied with the measured frequency difference.
This clearly demonstrates the cross-talk you mentioned, both between
the two counter inputs and between the inputs and the counter
reference OCXO
As my goal is to create a dual input timestamping counter that can
reliably measure with 1e-9 accuracy (both short and long term) there
is clearly some work to do.
Erik.
On 3-2-2022 17:14, Magnus Danielson via time-nuts wrote:
Erik,
You should be aware that cross-talk of transitions is a factor here.
It "pulls" the transition to the time-base clock.
It can be worth evaluating this by delaying the time-base clock in
controlled manor and measure non-linearity of the time-stamps.
A similar test is done between two inputs, as the trigger inputs can
cause cross-talk from one another. This is known to be the issue of
several vendors counters.
As you push the limit for the resolution, these effects tends to
increase in relative size, but for other work they can be fairly
ignored.
For some reason I have built a collection of pulse-generators and
delay mechanisms to increase the ability to test this. :)
Cheers,
Magnus
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