Thanks for the response. I looked at the documentation of OpenOCD. It is 
used for flashing firmware on the board and for debugging purposes using 
GDB. In the diagram below, advanced JTAG bridge can be replaced by OpenOCD 
and make the system more efficient. This is because OpenOCD is well 
maintained and provides a lot of advantages over Advanced JTAG Bridge. 

Currently, I am looking at different implementations of adv_dbg_sys.
I looked at this implementation of 
adv_dbg_sys: https://github.com/pulp-platform/adv_dbg_if
This code is implemented in system verilog and replaced Wishbone 
architecture with AXI.  It follows a modular architecture to build the 
system. 

SInce, the project is quite diverse and a lot of things can be done, it 
would be great if I could get a rough outline for the project.

Thanks
Shivam Aggarwal



On Monday, March 12, 2018 at 8:07:14 PM UTC+5:30, Carl Karsten wrote:
>
>
> Hi Shivam,
>
> Thanks for the time spent on this, it looks very promising. 
>
> I am not the best person to answer your questions, but I can give some 
> good guesses.  I'm sure someone else will soon, but for now...
>
>
> On Sun, Mar 11, 2018 at 8:58 AM, SHIVAM AGGARWAL <shiva...@iiitd.ac.in 
> <javascript:>> wrote:
>
>> Hi, 
>>
>> I have successfully set up the development environment. Here’s the link: 
>> https://pasteboard.co/HboNPNB.png
>>
>> I am currently reading about issue #39 
>> <https://github.com/timvideos/getting-started/issues/39>, to create a 
>> generic debug interface for soft-CPU cores and connect to GDB.
>>
>> Progress so far
>>
>>
>>    1. 
>>    
>>    I read about advanced debug system from openCores 
>>    <https://opencores.org/usercontent,doc,1270062172>. The document 
>>    elaborates the debugging system for OpenRisc-1000 Based systems. The 
>>    document provides information to support debugging both during simulation 
>>    as well as directly on the hardware.
>>    2. 
>>    
>>    I also read about JTAG and wishbone specifications.
>>    
>>
>>
>> The doc illustrates the following diagram to build hardware level 
>> debugging system.
>>
>>
>> Queries:
>>
>>    1. 
>>    
>>    Is it acceptable to re-use the above approach implemented by 
>>    OpenCores given in the attached document?
>>    
>>
> re-use is fine.    
>
>  
>
>>
>>    1. 
>>    
>>    Do we need support for multiple softCPU cores at the same time? 
>>    
>>
>
> I don't think so.
>  
>
>>
>>    1. 
>>    
>>    Can we use a MUX to switch between different softCPU cores?
>>    
>>
> Sorry, this is beyond my understanding of this project. 
>
>  
>
>>
>>    1. 
>>    
>>    After looking at the schematic of Numato Opsis board, I think 
>>    standard JTAG TAP implementation is used. Is that correct?
>>    
>>
> correct.
>
> Howerver, ""...running both on real hardware and in simulation." means a 
> VM like QEMU which does not have a JTAG.   If implementation with JTAG is 
> easier, then that would be a good first step. 
>  
>
>>
>>    1. 
>>    
>>    Do I need to implement the project in Migen?
>>    
>>
> I suspect it is preferred.  If there is a good reason to do something 
> else, you will have to explain why it is better.
>
>  
>
>>
>>    1. 
>>    
>>    I also looked at the documentation of OpenOCD but couldn’t understand 
>>    how it will be used for the project. Any help on that part?
>>    
>>
>
> OpenOCD is used to load the firmware file from disk onto the board.
>
>  
>
>>
>> Things to do:
>>
>>
>>    1. 
>>    
>>    To look into the internal working of each module. How each module 
>>    will interact with one another? 
>>    2. 
>>    
>>    How to build an efficient system to support multiple soft-CPU cores? 
>>    
>>
>> Please provide your valuable suggestions for the project.
>>
>> Thanks
>>
>> Shivam Aggarwal
>>
>> Potential GSOC Student
>>
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>
>
>
> -- 
> Carl K
>
>

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