On Sat, 10 Nov 2012 16:33:33 +0100, Daniel Glöckner wrote:
On Wed, Nov 07, 2012 at 04:18:00PM +0100, Thomas Preud'homme wrote:
Le mercredi 7 novembre 2012 16:09:51, Milutin Jovanović a écrit :
> Other then that, looks OK to me. BTW, I did not check correctness,
just
> reviewed the style and logic.
Don't worry for the correctness. GOT needs to be aligned on 4 bytes
on ARM so
I know it's fine. I tested the code successfully on ARM and it
yields the
correct result on my tests.
Can we assume GOT entries are aligned to 2 bytes on all
architectures?
In fact currently in tcc, GOT entries are all at least 4 bytes aligned.
Indeed, s1->got->data_offset is always incremented by PTR_SIZE which is
4 or greater. Thus I could use the new structure unconditionnally and
add a #if PTR_SIZE < 2 #error + a check in section_ptr_add to unsure we
catch any changes of how GOT entries are aligned. That would make for a
much smaller patch and more consistent situation.
Any thought people?
By the way, why is the following code used in fill_got_entry:
offset = get_got_offset(s1, sym_index);
section_reserve(s1->got, offset + PTR_SIZE);
when section_ptr_add(s1->got, PTR_SIZE) would have the same effect?
Daniel
Best regards,
Thomas
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