Le mercredi 1 mai 2013 21:14:08, Daniel Glöckner a écrit : > On Wed, May 01, 2013 at 05:02:54PM +0200, Thomas Preud'homme wrote: > > Le mercredi 1 mai 2013 16:59:25, Daniel Glöckner a écrit : > > > In my 2nd edition ARM ARM this maps to the FSTMS instruction and there > > > is a note allowing implementations to keep the values in an internal > > > representation and just convert them to IEEE format for storing to > > > memory. So I don't think we can use this instruction to store double > > > arguments and need one FSTMS/FSTMD for each run of consecutive fpu > > > registers of same precision to be stored. Or have read otherwise? > > > > Nope, I didn't see that line. Please go ahead if you want to fix it, > > otherwise I'll do it later (I'm working right now). > > I did some more research. > > ARM ARM 2nd edition (= Issue E) has several paragraphs below figure 2-1 > in chapter C2 talking about that no assumptions can be made as to how > single-precision registers overlap double-precision registers and that > the value of double-precision registers after their corresponding single- > precision registers have been loaded with a value becomes UNPREDICTABLE. > > Issue I, which can be downloaded after registering with ARM, replaces > that half page of text with > "The mapping between a double-precision register and its pair of > single-precision registers is as follows: > - S<2n> lies in the least significant half of D<n> > - S<2n+1> lies in the most significant half of D<n>."
That's what I read in my manual indeed. Or maybe I read it in AAPCS. > > So we are safe with the current implementation, at least on little-endian > ARM. On big-endian ARM the halves will have the wrong order if we don't > use FSTMD, but there is a lot more that needs to be done until we support > big-endian ARM. Do you know where big-endian is used and by who? There once was a port of Debian for ARM big endian but it never got much traction so it seems to me there is not much interest for such a port anyway. > > Daniel Best regards, Thomas
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