Just had a breakthrough here.  We were using the SMCLK for sample conversion.  We switched to ACLK and things tightened right up.  We've managed to start sampling (typically...) within 1-2 ticks of the ACLK.

But to answer your question, yes, it is cumulative. 

;)

-M

On 10/25/05, Michael Schippling <[EMAIL PROTECTED]> wrote:
Wow, 1.3% error in your time sync...seems pretty good to me.
But I guess it's cumulative, eh?

I might suspect something causing you to miss a timer interrupt,
maybe the transmit task or something? You might try flashing the
LED on each sample and looking for a missing pulse with a logic
analyzer.

MS

Mike Deneen wrote:
> Hello,
>
> I have managed to implement the Vanderbilt Time Sync code along with
> ADC-DMA code with the intent of streaming 1khz adc samples to a base
> station.  I have the ADC set up to sample at 1khz and then switch
> buffers.  The full buffer is processed and sent out in a 128 byte packet.
>
> Right now, experimenting with two, I have read the global time, started
> sampling, finished sampling, read the global time again.  With two motes
> taking 73 samples/buffer there is a finishing time difference of up to a
> millisecond.
>
> Is the ADC really sampling at 1khz?  Is there a better way to align the
> motes?  How much drift is expected?  It is important for me to sample at
> the same time, mote to mote.
>
> Thanks for any insight you can give.
>
> -Mike
>
>
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