With the default configuration (that you use) I verified in the
debugger that in Usart.setModeSpi (in HplMsp430Usart0P.nc) the USART
Transmit Control Register U0TCTL is set to 0xA3, i.e. ckph and ckpl
flags are set correctly.
With this configuration (ckph=1, ckpl = 0) data is written at falling
edge, because UCLK is delayed by one half cycle. I think you should
rather use ckph=0 and ckpl = 0 instead, then data is written at rising
edge and stable at falling edge (see Figure 14−9 MSP430 User's Guide).
Jan
On Fri, Jul 18, 2008 at 1:56 AM, Xiaofan Jiang
<[EMAIL PROTECTED]> wrote:
> Hi,
>
> I've been working on a driver to talk to a SPI slave from a Telos master.
> The slave uses the CPOL=0, CPHA=1 convention (clock polarity is base 0 and
> data delayed from clock by half clock). The data should change on rising
> edge of clock and read/written on fallen edge.
>
> This corresponds to the default parameters set in msp430usart.h:
>
> msp430_spi_union_config_t msp430_spi_default_config = {
> {
> ubr : 0x0002,
> ssel : 0x02,
> clen : 1,
> listen : 0,
> mm : 1,
> ckph : 1, // <---- CPHA=1
> ckpl : 0, // <---- CPOL=0
> stc : 1
> }
> };
>
> However, using an oscilloscope, I observed that the clock phase is not
> correct. The data is half a cycle early (data is read/written on rising edge
> of clock instead of falling).
>
> Any help on why this is happening and where to fix it is greatly
> appreciated.
>
> Thanks!
> -Fred
>
>
_______________________________________________
Tinyos-help mailing list
[email protected]
https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help
