We have discovered a time-synchronization bug in the TinyOS code. The error can be reproduced with the attached code.
Bug description: On the XBow IRIS platform, when hardware acknowledgements are enabled, the node receiving a time synchronization message will in fact receive the time stamp with a value corresponding to t - 7ms (so there is a constant -7ms time shift). This bug has been observed with the most recent CVS tinyos version. Reproduction: The attached code will make a mote with NodeID 0 the synchronization master node, and a mote with NodeID 1 the slave node. The master node will send every 10s a time synchronization code. Both the master and the slave nodes will enable PortF6 (Pin 3 on the JTag header of the MIB520, Pin 10 being the ground) for about 10ms each cycle. These pins can then be used on an oscilloscope or logic analyzer to measure the synchronization error. When hardware acks are enabled, the synchronization error is -7ms (plus noise); when hardware acks are disabled, the synchronization error is 0ms (plus noise). Any idea on how to fix that bug is very appreciated. *Linh
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