Thanks for the reply. I did dabble with the idea of using more than one communication's line, but the project I am working on would prefer there to be a single comm line with another line acting as a software controlled clock. Essentially I would be using a shift register to pass each bit of the address and data packet through the gpio into the fpga. Have you or anyone had any experience in something like this?
Paimon Sorornejad Computer Sciences Corporation, P&W East Hartford, CT, Engineering Building, 2nd Floor, ColD16 Phone: (860)-565-1665 [email protected] _______________________________________________ Tinyos-help mailing list [email protected] https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help
