2012/1/7 Xiaohui Liu <[email protected]> > Hi, > > A follow-up question is: how to know what other interrupts are masked when > an interrupt occurs? >
1) you need to study the cpu manual and understand how the interrupt system works. 2) you need to understand how the low level s/w works and what state it leaves the cpu in with respect to the interrupts. > Thanks again. > > 2012/1/7 Xiaohui Liu <[email protected]> > >> Hi, >> >> Thank you very much for your kind response. >> >> Where can I check which category, atomic or not, an interrupt falls into? >> In msp430, I understand there are TOSH_SIGNAL and TOSH_INTERRUPT, which are >> equivalent to AVR_ATOMIC_HANDLER() and AVR_NONATOMIC_HANDLER(). But how do >> I find out if an interrupt is the former or the latter? >> >> Look forward to any clarification, which I'm sincerely grateful for. >> >> 2012/1/6 András Bíró <[email protected]> >> >>> Hi, >>> >>> First of all, there are two interrupt handler macro (at least on AVR): >>> AVR_ATOMIC_HANDLER() and AVR_NONATOMIC_HANDLER(), obviously the first >>> one disables the global interrupts, the second one doesn't. Most of >>> the drivers uses the atomic one, you have to handle much more error >>> possibility in the non-atomic one, usually the atomic is more >>> effective. >>> >>> However most driver doesn't handle the whole interrupt in atomic. For >>> example, on receive, the radio will download the message into the ram, >>> sets up timestamps, sends an ack if needed, then exits the atomic >>> content with posting a task. After that it does some message >>> formatting, and signals the Receive.receive event in non-atomic >>> context. >>> >>> You will also receive most of the interrupts when exiting from the >>> atomic section: on most MCUs, an interrupt will set a flag. If the >>> flag is set while the global interrupts are disabled (atomic), the >>> interrupt will occour when you enable the global interrupts. The only >>> problem is if you receive more than one of the same interrupt: in that >>> case, you'll only get the last one. >>> >>> Interrupt priority: it depends on the MCU, check the datasheet. On the >>> AVRs, the lower interrupt vector address means higher priority. >>> >>> Andris >>> >>> On Fri, Jan 6, 2012 at 9:37 PM, Xiaohui Liu <[email protected]> wrote: >>> > Hello everyone, >>> > >>> > When an interrupt occurs (e.g. packet reception), its ISR is going to >>> be >>> > executed. What will happen if another interrupt (e.g. another packet >>> > reception or timer fires) occurs before the ISR for the previous >>> interrupt >>> > finishes? If the ISR is preempted, then interrupts can be nested and >>> the >>> > last interrupt will always be served first? If it depends on the >>> priorities >>> > of these interrupts, where can I find their priorities? Any >>> explanation will >>> > be highly appreciated. >>> > >>> > -- >>> > -Xiaohui Liu >>> > >>> > _______________________________________________ >>> > Tinyos-help mailing list >>> > [email protected] >>> > >>> https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help >>> >> >> >> >> -- >> -Xiaohui Liu >> > > > > -- > -Xiaohui Liu > > _______________________________________________ > Tinyos-help mailing list > [email protected] > https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help > -- Eric B. Decker Senior (over 50 :-) Researcher
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