Hi
Eric is right with the comments on the SD performance.
Just to add that I think the problem is not on FatFS but on the SD driver that
does not support
multiples writes; please see the last diagram in
http://elm-chan.org/docs/mmc/mmc_e.html.
At the time we made the measurements I did not know how to modify thar part of
the driver.
Regards,
André
----- Original Message -----
From: Eric Decker
To: Avishay Meron
Cc: steve ayer ; [email protected]
Sent: Wednesday, January 02, 2013 9:54 AM
Subject: Re: [Tinyos-help] Shimmer SD write speed
On Mon, Dec 31, 2012 at 2:55 PM, Avishay Meron
<[email protected]> wrote:
Hi all.
Searching google and the mailing list, I haven't found an explicit answer
to my problem. Here goes:
I'm trying to test SD logging max write speed on a shimmer2r. I've tried
using the FatFS but got unsatisfying results.
So, I decided to write directly to the SD. Using a simple application (see
code below), I found that the max rate of SD writing is about 20kB/s. Is that
it? is this the maximum rate possible? I was hoping to get at least 0.5 or 1
MB/s. Any suggestions?
It looks like the Shimmer uses the default x1 DCOSpec settings which is main
cpu clock at 4MiHz and SMCLK MCLK/4 -> 1MiHz. Steve can you verify that?
I looked at the paper Andre sent. That CPU is being clocked at 16MHz, and
the SPI clocked at 4 MHz and they are seeing about 120 KB/s. The Shimmer is
clocking the SD at 1/4 that speed .... 30KB/s. So the 20KB/s isn't
unreasonable.
Okay. Why?...
SPI is a serial bus and it is being clocked at 1 MiHZ. 8 bits takes 1
MiHZ/8 Bytes/s so this yeilds a theoretical max of 131,072 B/s (about
128KiB/s). But that is if one is running the bus full time. Which isn't
going to happen.
Now you've eliminated the overhead of the FatFS and are writing directly to
the card. I'm at a loss why you are losing about a factor of 6. I wouldn't
have guessed it was that bad. The SD protocol running in SPI mode does have a
bunch of overhead, so it most likely the culpirit. I also don't know if the
Shimmer folks have done a tuning pass. Performance tuning requires a fair
amount of skill.
Now one quick test you can do is change the clock relationship. In the
current tinyos-main (as of 4449bba, master), MCLK (DCO) is 4 MiHz, SMCLK
divisor is /4, and the TA divisor (usec ticker) is /1. If you change these to
SMCLK divisor /1 and TA divisor to /4 the SPI will now get clocked at 4 MiHZ
and TA will still be at 1 uis (1 binary micro second).
You should see the raw SD performance go from 20KiB/s to around 80KiB/s. It
should be linear.
Now doing this experiment on the current tip of the trunk is rather painful
because the knobs are spread around all over the place.
One of the things I did when I cleaned the core up was I fixed this. I
would recommend you shift over to using my new msp430 core. It lives at
https://github.com/tp-freeforall/prod(tp-master). There is a simple spec file
(DcoSpec.h) that specifies all the relationships.
You would have to override the default file that comes from tos/chips/msp430
with a platform specific one.
Happy new year to you all...
--
Eric B. Decker
Senior (over 50 :-) Researcher
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