I resend the email since replied to the author only the first time. Ugo
2014-10-19 11:31 GMT+02:00 Ugo Maria Colesanti <[email protected]>: > Hi Andreas, > please find attached the diff file of the rfa1/rfr2 datasheets that I made > some months ago, I think that it might be useful. We have developed a > platform based on the RFA1 and are planning to upgrade it with the RFR2 by > the end of the year more or less. From my analysis, the rfa1 tinyos code, > except for the ADC part, is fine for the rfr2 too if you don't use any > additional functionality that the rfr2 provides. I just added two commands > to enable the low power features of the radio in rx and that's it. I did > not noticed that the RX_OVERRIDE feature was enabled by default. > Hope it helps, > > Ugo Colesanti > > >>>>>>>>>>>>> ATTACHED FILE Chapter 1-6: No changes except obvious ones. Chapter 7: AVR CPU Core ----------------------- -> [RFR2 - 7.6.4] EIND – Extended Indirect Register - is mentioned in RFR2 (in register summary too) but not in RFA1. However in the branch instructions [RFR2 - 34.2 and RFA1 - 34.2]it is present in both datasheets. Jump over 128kb? it is not mentioned in the remainder of the datasheet. Chapter 8: AVR Memories ------------------------ -> [RFR2 - 8.1] In-System Reprogrammable Flash Program Memory - "The application section of the Flash memory contains 3 user signature pages. These pages can be used to store data that should never be modified by an application program e.g. ID numbers, calibration data etc. For details see section "User Signature Data" on page 507." -> [RFR2 - 8.3.1] EEPROM Read Write Access - "The programming time can be reduced if an entire 8 byte EEPROM page is programmed instead of single bytes." -> [RFR2 - 8.4.4 EECR] – EEPROM Control Register - Bit 5:4 – EEPM1:0 - EEPROM Programming Mode - there is the page buffer load (See previous note) Chatper 9: Low-Power 2.4 GHz Transceiver ---------------------------------------- -> [RFR2 - 9.3.1.1] Register Access - The note related to register updates when the radio is not in TRX_OFF has disappeared in RFR2 -> problem solved? The note in RFA1 was: "It is recommended to modify the transceiver registers in the address range 0x141 - 0x14D and 0x155 - 0x17F only, while in TRX_OFF state. In this case, no special procedures are required. If registers are written while the transceiver is not in TRX_OFF state (e.g. PLL_ON,RX_LISTEN, TX_ACTIVE, ...) a separate update request for the internal temporary registers is needed. Read back of the registers does not necessarily reflect the state of the internal temporary registers. The values returned show merely the previously written content. The update request can be forced by either these two: 1. Repeat the write to the last written register or 2. Read and write back register PART_NUM." -> [RFR2 - 9.3.4] TX Start Interrupt - The txstart is present in RFR2 but not in RFA1. WARNING: this interrupt signal the start of the preamble, not SFD!!! -> [RFR2 - 9.4.2.5] MAF – Multiple Address Filter is present in RFR2 but not in RFA1. "The address filter was extended to support four PANs." There are Additional register set for Multiple Address Filter. It might be used in extended operating mode. Not in the current driver that only uses basic operating mode. -> [RFR2 - 9.6.2.4] TX Power Ramping - WARNING: external front end management has changed, there is the PARCR register instead of PHY_TX_PWR register. Additional options to control external PA: "When using en external RF front-end (refer to "RX/TX Indicator" on page 97) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved by PARCR register in the bits PALTU/PALTD." -> [RFR2 - 9.6.2.5] TX Spectrum side lobe suppression - Lobe suppression is present in RFR2 but not in RFA1, it's an interesting feature when using a front end. -> [RFR2 - 9.6.6.5] RF Channel Selection - "Additionally, the PLL supports all frequencies from 2322 MHz to 2527 MHz with 500 kHz frequency spacing. The frequency is selected by CC_BAND (see "CC_CTRL_1 – Channel Control Register 1" on page 135) and CC_NUMBER" -> [RFR2 - 9.8.9] Receiver Override - "When an incoming received frame is overlayed by a later starting stronger signal, the overlayed signal would surely destroy the received frame. With an enabled RX Override feature, the receiver breakes the reception and restarts synchronisation to the stronger signal. The IRQs are set like after reception of a wrong FCS.The feature RX Override is enabled if the bit RX_OVERRIDE in register RX_SYN is set.". It's a very interesting feature, however there are some control registers not well documented (see later) -> [RFR2 - 9.8.10] Reduced Power Consumption Mode (RPC) - "The RPC mode of the ATmega256/128/64RFR2 offers a variety of independent techniques and methods to significantly reduce the power consumption of the radio transceiver. RPC is applicable to selected operating modes and is transparent to other extended features.". This is the main difference w.r.t. RFA1. -> [RFR2 - 9.8.11] Phase Difference Measurement - is present in RFR2 but not in RFA1 (don't know what is useful for...) -> [RFR2 - 9.12.7] TRX_CTRL_0 - phase measurements register present in RFR2 but not in RFA1 -> [RFR2 - 9.12.8] TRX_CTRL_1 – Transceiver Control Register 1 - Bit 4 – PLL_TX_FLT - Enable PLL TX Filter is present in RFR2 but not in RFA1 (see lobe suppression) -> [RFR2 - 9.12.9] PHY_TX_PWR – Transceiver Transmit Power Control Register - Bit 7:6 – PA_BUF_LT1:0 - Power Amplifier Buffer Lead Time (lead time internal PA buffer to control external front-end, relative to internal PA), Bit 5:4 – PA_LT1:0 - Power Amplifier Lead Time (lead time of the internal PA rlative to transmitted frame SHR) are present in RFA1 but not longer in RFR2 -> [RFR2 - 9.12.10] PARCR – Power Amplifier Ramp up/down Control Register - lead time of external PA and frequency inversion. It has replaced the 4 MSB in PHY_TX_PWR used in RFA1. -> [RFR2 -9.12.15] RX_CTRL – Transceiver Receive Control Register - settings reserved for internal use -> [RFR2 - 9.12.20] IRQ_MASK1 – Transceiver Interrupt Enable Register 1 - interrupts related to TX_START and additional address filters (0..3) -> [RFR2 - 9.12.22] IRQ_STATUS1 – Transceiver Interrupt Status Register 1 - see previous comment -> [RFR2 - 9.12.26] RX_SYN – Transceiver Receiver Sensitivity Control Register - Bit 6 – RX_OVERRIDE - Receiver Override Function - Bit 5 – RXO_CFG1 - RX_OVERRIDE - Bit 4 – RXO_CFG0 - RX_OVERRIDE (not documented) -> [RFR2 - 9.12.25] FTN_CTRL – Transceiver Filter Tuning Control Register - additional fields but reserved for internal use -> [RFR2 - 9.12.26] PLL_CF – Transceiver Center Frequency Calibration Control Register - additional fields but reserved for internal use -> [RFR2 -9.12.30] PLL_DCU – Transceiver Delay Cell Calibration Control Register - additional bits reserved for internal use -> [RFR2 - 9.12.31] CC_CTRL_0 – Channel Control Register 0 - sets the channel number - see 9.6.6.5 RF channel selection -> [RFR2 -9.12.32] CC_CTRL_1 – Channel Control Register 1 - sets the band (only updated if CC_CTRL0 is written) - see 9.6.6.5 RF channel selection -> [RFR2 - 9.12.33] TRX_RPC – Transceiver Reduced Power Consumption Control - see 9.8.10 Reduced Power Consumption Mode (RPC) -> [RFR2 - from 9.12.54 MAFCR0 – Multiple Address Filter Configuration Register 0 to 9.12.71 MAFSA3L] – Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) - additional register for address filtering (0..3) -> [RFR2 - 9.12.72 TST_CTRL_DIGI] – Transceiver Digital Test Control Register - additional bits but for internal use only -> [RFR2 - 9.12.74 TST_AGC] – Transceiver Automatic Gain Control and Test Register - automatic gain control settings (don't know the effects of these settings...) -> [RFR2 - 9.12.75 TST_SDM] – Transceiver Sigma-Delta Modulator Control and Test Register - sigma delta modulator settings (don't know the effects of these settings...) Chapter 10: MAC Symbol Counter ------------------------------ -> [RFR2 - 10.11.1] Symbol Counter Compare Source Register (SCCSR) exists in rfr2 but not in RFA1: "The Register describes the source timestamp register used for the relative compare mode. The time stamp source can be selected separately for each compare unit. Possible sources for the relative compare are the Transmit Timestamp, the Receive Timestamp or the Beacon Timestamp (default)" -> [RFR2 - 10.11.10-13] Symbol Counter Transmit Frame Timestamp Register (SCTSTRxx) exists in rfr2 but not in rfa1: "The Transmit Frame Timestamp Register is updated one symbol before the beginning of the frame transmission (preamble transmission). To allign the Transmit Frame Timestamp with a Received Frame Timestamp (SFD Timestamp),a fixed offset of 11 symbols (1 Symbol Startup + 8 Symbols Preamble + 2 Symbols SFD) need to be added to the Transmit Timestamp." -> [RFR2 - 10.11.14-17] Symbol Counter Received Frame Timestamp Register (SCRSTRxx) exists in rfr2 but not in rfa1: "The Received Frame Timestamp Register is updated at the end of the frame reception with the contents of the Frame Timestamp Register (SFD timestamp) if the received frame was valid (FCS ok). If the transceiver auto modes are enabled and address filtering is active, the Received Frame Timestamp is only updated, if there was an address match also." -> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 5 – SCBTSM - Symbol Counter Beacon Timestamp Mask Register exists in rfr2 but not in rfa1: "This bit must be set to disable automatic beacon timestamping. All other timestamps as well as manual beacon timestamping is not effected by this setting." -> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 4:2 – SCCKDIV2:0 - Clock divider for synchronous clock source (16MHz Transceiver Clock) exists in rfr2 but not in rfa1: "The 3 Bit value controls the symbol counter clock prescaler. The input clock to the prescaler is the 16MHz transceiver clock. The different prescaler values are defined in the table below. The default prescaler setting is 62.5kHz. If the transceiver clock is selected, the counter continues on the RTC time base during sleep mode, regardless of the SCCKDIV setting." -> [RFR2 - 10.11.35] in Symbol Counter Control Register 1 (SCCR1): Bit 1 – SCEECLK - Enable External Clock Source on PG2 exists on rfr2 but not on rfa1: "If this bit is set, a asynchronous clock provided on PG2 can be used to run the symbol counter. SCEECLK overrieds SCCKSEL and forces the selection of the external clock source. The clock source on PG2 can have a maximum frequency of 1/4 of the controller clock speed. If selected, the clock on PG2 is used during sleep mode also." Chapter 11: System Clock and Clock Options ------------------------------------------ no changes Chapter 12: Power Management and Sleep Modes --------------------------------------------- -> [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 3 – ATBE - Analog Test-bus Enable is present in rfr2 but not in rfa1: "The analog test-bus can be enabled by setting this bit to one. The test-bus can only be activated in the test-mode. Internal analog signals are then available at the TSTOP,TSTON, TSIP and TSTIN pins" -> [RFR2 - 12.6.5] Transceiver Pin Register (TRXPR): Bit 2 – TRXTST - Transceiver Test-mode Enable is present in rfr2 but not in rfa1: "The TRXTST bit enables the test-functionality of the transceiver. In addition the general device test-mode must be enabled by applying the appropriate test-signature." -> [RFR2 - 12.6.6] Data Retention Configuration Register #0 (DRTRAM0) – Bit 3:2 – DRTMP1:0 - Positive Data Retention Voltage Setting // Bit 1:0 – DRTMN1:0 - Negative Data Retention Voltage Setting -> [RFR2 - 12.6.7] Data Retention Configuration Register #1 (DRTRAM1) - idem -> [RFR2 - 12.6.8] Data Retention Configuration Register #2 (DRTRAM2) - idem + Bit 7 – DISPC - Disable Power-chain of SRAM 2 -> [RFR2 - 12.6.9] Data Retention Configuration Register #3 (DRTRAM3) - idem Chapter 13: System Control and Reset ------------------------------------ no changes Chapter 14: I/O-Ports --------------------- no changes Chapter 15: Interrupts ---------------------- Interrupt vector table -> there are TX_START and ADDRESS matching interrupts at the end of the table on the rfr2 that are missing from rfa1. Interrupt addresses changes accordingly based on the presence of boot section. The new interrupts are at the end. Chapter 16: External Interrupts ----------- no changes Chapter 17: 8-bit Timer/Counter0 with PWM ----------------------------------------- no changes Chapter 18: 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) ---------------------------------------------------------------- no changes Chapter 19: Timer/Counter 0, 1, 3, 4, and 5 Prescaler ----------------------------------------------------- no changes Chapter 20: Output Compare Modulator (OCM1C0A) ---------------------------------------------- no changes Chapter 21: 8-bit Timer/Counter2 with PWM and Asynchronous Operation -------------------------------------------------------------------- no changes Chapter 22: SPI- Serial Peripheral Interface -------------------------------------------- no changes Chapter 23: USART ----------------- no changes Chapter 24: USART in SPI Mode ----------------------------- no changes Chapter 25: 2-wire Serial Interface ----------------------------------- no changes Chapter 26: AC – Analog Comparator ---------------------------------- no changes Chapter 27: ADC – Analog to Digital Converter --------------------------------------------- Too many changes in this chapter, analyze it later. Chapter 28: JTAG Interface and On-chip Debug System --------------------------------------------------- no changes Chapter 29: IEEE 1149.1 (JTAG) Boundary-scan -------------------------------------------- no changes Chapter 30: Boot Loader Support – Read-While-Write Self-Programming -------------------------------------------------------------------- [RFR2 - 30.6.14] Boot Loader Parameters for 64 kByte of Flash Memory -> is present in rfr2 but not in rfa1 [RFR2 - 30.6.16] Boot Loader Parameters for 256 kByte of Flash Memory -> is present in rfr2 but not in rfa1 Chapter 31: Memory Programming ------------------------------- [RFR2 - 31.4] User Signature Data -> present in rfr2 but not in rfa1 [RFR2 - 31.6] Page Size -> different values for different sizes in rfr2 [RFR2 - 31.8.15] Chip Erase of EEPROM only -> is present in rfr2 but not in rfa1 [RFR2 - 31.8.16] Erase EEPROM Page -> is present in rfr2 but not in rfa1 [RFR2 - 31.8.17] Writing User Signature Data -> is present in rfr2 but not in rfa1 [RFR2 - 31.8.18] Erasing User Signature Data -> is present in rfr2 but not in rfa1 [RFR2 - 31.8.19] Reading User Signature Data -> is present in rfr2 but not in rfa1 [RFR2 - Table 31-19] Chip Erase EEPROM only/Enter EEPROM Erase/Enter User Signature Page Write/Enter User Signature Page Erase/ instruction present in rfr2 but not in rfa1 [RFR2 - 31.10.25] Performing Chip Erase of only the EEPROM -> is present in rfr2 but not in rfa1 [RFR2 - 31.10.26] Erasing an EEPROM Page -> is present in rfr2 but not in rfa1 [RFR2 - 31.10.27] Programming User Signature Data -> is present in rfr2 but not in rfa1 [RFR2 - 31.10.28] Erasing User Signature Data -> is present in rfr2 but not in rfa1 [RFR2 - 31.10.29] Reading User Signature Data -> is present in rfr2 but not in rfa1 Chapter 32: Application Circuits -------------------------------- ignored Chapter 33: Register Summary ---------------------------- need to have a look to the register summary Chapter 34: Instruction Set Summary ----------------------------------- no changes (instruction set is identical) >>>>>>>>>>>>>>>>>> END ATTACHED FILE > 2014-10-17 16:39 GMT+02:00 Andreas Weigel <[email protected]>: > >> Hi everyone, >> >> Suggestion: Add the following line somewhere to the init code: >> RX_SYN &= ~(1 << 6); >> >> Rationale: >> I just had some "fun time" with a self-made C-port (not very beautiful, >> but it does its job) of the atm128rfa1 RFA1DriverLayerP (and the >> corresponding rfxlink layers). >> >> Letting four ATmega256rfr2-based nodes send out broadcast packets as >> fast as possible (having the whole stack in place, including backoffs >> etc.), lead to RADIO_ASSERT(!radioIrq) being triggered in the RX_END >> ISR. After some happy debugging and thinking (is my protocolstack >> actually to slow in processing the tasklet code stuff?) I was sure that >> this should not be possible. >> >> I then stumbled across a new and greatly-documented feature of the rfr2 >> named RX_OVERRIDE, which is enabled on this chip by default (who does >> such things?). This seems to lead to RX_END interrupts which are >> triggered very soon (< 20 us) after the corresponding RX_START. In rare >> circumstances when RX_START was interrupted again by the RadioAlarm >> interrupt (and correspondingly, the TosRandomCollisionLayer >> RadioAlarm.fired() code was executed), service_radio got deferred long >> enough to allow for the RX_END to occur and the RADIO_ASSERT to happen. >> Deactivating RX_OVERRIDE solved the problem. >> >> I do not know (as I could not try out or know how fast the actual TinyOS >> stack handles the code), if this problem would really affect an >> ATmega256rfr2 running TinyOS (which I did not), but I think it at least >> very possible. Considering this, I suggest to add the code shown above >> to the init function of the driver to make the current radio driver safe >> for all rfr2-type chips (also in case someone "ports" the code to rfr2 >> and is -- like me -- unaware of this new feature), so that other people >> are spared the pain I just lived through during the last few days >> >> Regards, >> Andreas >> _______________________________________________ >> Tinyos-help mailing list >> [email protected] >> https://www.millennium.berkeley.edu/cgi-bin/mailman/listinfo/tinyos-help >> > >
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