This patchset adds support for H1 Secure Microcontroller running Cr50 firmware. It implements several functions, including TPM-like functionality, and communicates over SPI using the FIFO protocol described in the PTP Spec, section 6. H1 is a proprietary chip that the Chrome OS team is investigating for inclusion in future Chromebooks.
Depends on the following patchset: - tpm_tis_core: add optional max xfer size check v2: Removed driver-specific sysfs attributes. Compatible id changed to cr50 from cr50_spi. Updated descriptions of the supported device/interface. v3: Fixed potential race-condition with last_access_jiffies. Started using tx_buf/rx_buf in cr50_spi_phy to avoid potential problems with DMA. Removed DT properties for fw timing parameters. Fixed style. v4: Fixed cacheline alignment for xfer buffers. Andrey Pronin (2): tpm: devicetree: document properties for cr50 tpm: add driver for cr50 on SPI .../devicetree/bindings/security/tpm/cr50_spi.txt | 21 ++ drivers/char/tpm/Kconfig | 9 + drivers/char/tpm/Makefile | 1 + drivers/char/tpm/cr50_spi.c | 350 +++++++++++++++++++++ 4 files changed, 381 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt create mode 100644 drivers/char/tpm/cr50_spi.c -- 2.6.6 ------------------------------------------------------------------------------ _______________________________________________ tpmdd-devel mailing list tpmdd-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/tpmdd-devel