On 8/14/2017 6:10 AM, Jarkko Sakkinen wrote:
Nuvoton, ST Micro, and Infineon confirmed that the TPM empties a byte from
the FIFO in under 1 usec. So, even with a static burst count, the entire
FIFO would empty in under 10 usec.
Does this break anything lets say in a decade time frame? If it does, I
will not even consider this. Can you give a definitive answer for that?
My attempt at predicting the future ...
1 - Clock speed should get faster, not slower, so the 1 usec wait state
should get shorter.
2 - TPM buffers should get larger. I'm already reading of 256 byte
buffers. So there should be fewer wait states.
3 - There is a trend toward using the CRB, making the FIFO less applicable.
4 - There is a trend away from LPC connected serial port devices,
printers, and PS/2 mouse and keyboard, and toward USB connected devices.
I assume this will continue, making the already insignificant wait
states irrelevant.
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