Roger,
As far as board layout, .020" T to R, and .030" T,R to Gnd. Not a
good idea to route a trace between the pins of an IC. If you have a
multi-layer board, submerging traces will let you use the dielectric
of the board to your advantage. If you are running Primary, you may
also consider controlled impedance.
If just a single layer, using opposite sides of the board will help
to give you the extra separation.
If you plan to use bypass capacitors, which you might have to if you
plan to meet FCC Class B, a couple of things:
1. Do not go above .47 pF combined capacitance per T,R lead.
May get into longitudinal balance problems if you go above that
unless you plan to match capacitors.
2. 1000 V ceramics should do. As you can see in 68.302 and .304
lotsa high voltages can appear.
If you plan to use ferrite beads or a toroid as a common mode choke,
you will either have to keep traces free from under the part or
insulate. Ferrite will break over given the extra voltage. Also
watch out for other 3-dimensional clearances.
I spoke to Bill vonAlven at the FCC this morning. ISDN NPRM is now at the
90 day waiting period.
"All opinions are mine & not necessarily those of my employer.
Eric Petitpierre
Pulsecom
Herndon, VA
[email protected]
______________________________ Reply Separator _________________________________
Subject: Part 68, board layout
Author: [email protected] at SMTP
List-Post: [email protected]
Date: 7/15/96 9:41 AM
Treggers,
I am looking for helpful hints about board layout and ISDN, PSTN connectors.
I can find no specification within Part 68 about layout requirements, but
there must be some 'rules of thumb' to elude problems with Part 68 testing.
All hints, references, or what not would be greatly appreciated.
advTHANKSance,
roger
[email protected]
"And forget not that
the earth delights to feel your bare feet and
the winds long to play with your hair."
- Kahlil Gibran
