David, I agree with what Eric has suggested, but add:
The most misunderstood circuits in a V.34 DAA are the holding circuit and 2W to 4W hybrid. And their effect on V.34 performance. The main thing to remember when designing a holding circuit for V.34 is the carrier frequency (1959) and symbol rate (3429). If one half of the symbol rate is subtracted from the carrier frequency you get a value of 244.5 Hz. This is the lower edge of the V.34 28.8 carrier. The holding circuit high frequency 3 dB cutoff must be at least an octave below 244.5 Hz or in other words no higher than 120 Hz. I prefer 60 Hz. The value of capacitor in the holding circuit will vary with the values used in the base of the darlington transistor and the detrimental effect on pulse dialing. I have used as high as 10 microfarad and a low as 0.33 Under no circumstances use a FET in place of the Darlington in a V.34 DAA. Unless you are willing to add some addition circuitry to eliminate the distortion that will occur in a fairly high percentage of the FETs. I think a 2.2 uf coupling capacitor is too small. It's reactance at 244.5 Hz is a problem. I never used anything lower than 4.7 and will usually use 6.8 uf. And have used as large as 22 uf. Transhybrid loss can also be a problem and the effect the local loop length has on it is not well understood by many engineers. The V.34 dsp code should remove a certain amount of the local echo. The combination of good dsp code and the compromise for an average line in the DAA generally works. I prefer to use an active hybrid to get the THL I want and let the dsp loaf until a very poor local loop is encountered. Hope this helps. Regards, Duane
