Jeff, I suggest you lay out your CPCI boards with multiple optional component locations (two per I/O port) for a 220 to 470 picofarad ceramic capacitors between signal ground and chassis ground. Make sure the caps go immediately by Via into the signal ground plane(s) then to the chassis ground (presumably, supplied by a metal D Shall connector or some nearby mounting bracket - you may want to build a wide chassis ground across the entire card edge under the external I/O connectors and mounting brackets).
Without this, you may find that non-shielded or marginally shielded I/O ports can fail Class A by about 10 dB, primarily from strong common mode PCI clock harmonics (66.6, 99.9 MHz ... ). I noticed that some CPCI vendors are using fully anodized card and chassis panels for their CPCI systems - a very bad idea - it will leave you without a decent chassis ground. This will yield the DC and low frequency AC isolation that the CPCI bozos wanted (apparently, CPCI was designed without any external EMC considerations), and get the 30 MHz+ coupling the rest of us need. So far this approach has worked well for our derivative of CPCI we call PXI, and with our PCI boards where the analog designers also want some degree of isolation below 10 MHz. Regards, Eric Lifsey Compliance Engineer National Instruments [email protected] on 01/26/98 11:12:20 AM Please respond to [email protected] To: [email protected] cc: (bcc: Eric Lifsey/AUS/NIC) Subject: CompactPCI I am seeking advise and comments concerning EMC testing and approval of CompactPCI chassis. My background is in personal computers and similar ITE equipment. The current practice is to tie logic ground and chassis ground together as often as possible. Many circuit boards tie logic ground and chassis ground together at every point where the board comes in contact with the chassis. The traditional notion of single point grounding has been shown time and again to be inadequate for preventing radiation in systems that are running frequencies of 100 MHz or faster. My concern is for the portion of the CompactPCI specification that requires that logic ground and chassis ( Frame ) ground be isolated from one another. Frame ground and logic ground can be tied together at only one point, the power supply. The specification even gives a value of 9M Ohms of impedance between logic and frame ground ( measured with a 100V DC source ). We are working on a CompactPCI chassis that will include; passive backplane, processor board, I/O companion board and power supply that will plug into the backplane. The chassis will have 7 slots for plug in cards that can be provided by anyone. Has anyone worked with a CompactPCI chassis built to this specification? Has anyone worked with similar constructions that employ similar grounding schemes? What problems can the single point grounding cause? Any comments or suggestions would be appreciated. Thanks in advance for your input. Jeff Busch Compliance Engineer [email protected] I-Bus 619-974-8470 San Diego 619-268-7863 fax
