On Thu, Aug 8, 2024 at 1:24 PM Pete Soper via TriEmbed
<triembed@triembed.org> wrote:
>
> (this time to all, with update)
>
> I just found out that running one m33f core and one RISCV core is an option.
>
> Eben Upton: "They're selectable at boot time: Each port into the bus fabric
> can be connected either to an M33 or a Hazard3 via a mux. You can even, if
> you're feeling obtuse, run with one of each."
>
> Source: https://www.theregister.com/2024/08/08/pi_pico_2_risc_v/
>
> Pete
>
> Aug 8, 2024 1:13:58 PM Mike Lisanke <mikelisa...@gmail.com>:
>
> Any idea Why they made the RISC-V cores Selectable from sw to switch with
> the ARM cores? Why not enable both? Conflicts?
> It's very interesting that an Open Source core now has potential to create
> RPi products.
>
> On Thu, Aug 8, 2024 at 1:09 PM Pete Soper via TriEmbed
> <triembed@triembed.org> wrote:
>>
>> https://www.raspberrypi.com/products/rp2350/
>>
>> Pete
I've always liked RISC. You made me switch to Fry mode and
preorder it through sparkfun, which led to 4 minutes of captcha.
Nobody accused me of being human, but WTF?
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