> -----Original Message-----
> From: Meng, Tingting <tingting.m...@altera.com>
> Sent: Tuesday, April 29, 2025 5:55 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Meng, Tingting <tingting.m...@altera.com>;
> Hea, Kok Kiang <kok.kiang....@altera.com>; Maniyam, Dinesh
> <dinesh.mani...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>;
> Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Rosdi, Danish
> Ahmad <danish.ahmad.ro...@altera.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.za...@altera.com>; Lim, Jit Loon
> <jit.loon....@altera.com>
> Subject: [PATCH v1 1/1] arm: socfpga: agilex5: Sub-device check enabled for
> runtime workaround
>
> From: Tingting Meng <tingting.m...@altera.com>
>
> Sub-device information is retrieved from the JTAG ID in Boot Scratch Cold 4
> Register. This interface is introduced to allow device-specific errata
> workarounds to be applied in the future, based on the detected sub-device
> type.
>
> Signed-off-by: Tingting Meng <tingting.m...@altera.com>
> ---
> arch/arm/mach-socfpga/misc_soc64.c | 32
> ++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-
> socfpga/misc_soc64.c
> index 4f080f4f0b3..5222b384434 100644
> --- a/arch/arm/mach-socfpga/misc_soc64.c
> +++ b/arch/arm/mach-socfpga/misc_soc64.c
> @@ -22,6 +22,22 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +/* Agilex5 Sub Device Jtag ID List */
> +#define A3690_JTAG_ID 0x036090DD
> +#define A3694_JTAG_ID 0x436090DD
> +#define A36C0_JTAG_ID 0x0360C0DD
> +#define A36C4_JTAG_ID 0x4360C0DD
> +#define A36D0_JTAG_ID 0x0360D0DD
> +#define A36D4_JTAG_ID 0x4360D0DD
> +#define A36F0_JTAG_ID 0x0360F0DD
> +#define A36F4_JTAG_ID 0x4360F0DD
> +#define A3610_JTAG_ID 0x036010DD
> +#define A3614_JTAG_ID 0x436010DD
> +#define A3630_JTAG_ID 0x036030DD
> +#define A3634_JTAG_ID 0x436030DD
> +
> +#define JTAG_ID_MASK 0xCFF0FFFF
> +
> /*
> * FPGA programming support for SoC FPGA Stratix 10
> */
> @@ -42,6 +58,22 @@ static Altera_desc altera_fpga[] = {
> },
> };
>
> +u32 socfpga_get_jtag_id(void)
> +{
> + u32 jtag_id;
> +
> + jtag_id = readl(socfpga_get_sysmgr_addr() +
> +SYSMGR_SOC64_BOOT_SCRATCH_COLD4);
> +
> + if (!jtag_id) {
> + debug("Failed to read JTAG ID. Default JTAG ID to
> A36F4_JTAG_ID.\n");
> + jtag_id = A36F4_JTAG_ID;
> + }
> +
> + debug("%s: jtag_id: 0x%x\n", __func__, jtag_id);
> +
> + return jtag_id;
> +}
> +
> /*
> * The Agilex5 platform has enabled the bloblist feature, and the bloblist
> * address and size are initialized based on the defconfig settings.
> --
> 2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@intel.com>
Best regards,
Tien Fong
