On 5/16/25 11:23, Venkatesh Yadav Abbarapu wrote:
The pcireg base is not assigned to any address, reading the pcireg base with PS_LINKUP_OFFSET which is incorrect and giving random values. So update the pcireg base from devicetree so that we can read the valid PCIE link status and PHY ready status. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbar...@amd.com> --- drivers/pci/pcie-xilinx-nwl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c index 7ef2bdf57b5..e03ab3be912 100644 --- a/drivers/pci/pcie-xilinx-nwl.c +++ b/drivers/pci/pcie-xilinx-nwl.c @@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie) return PTR_ERR(pcie->breg_base); pcie->phys_breg_base = res.start;+ ret = dev_read_resource_byname(dev, "pcireg", &res);+ if (ret) + return ret; + pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(pcie->pcireg_base)) + return PTR_ERR(pcie->pcireg_base); + ret = dev_read_resource_byname(dev, "cfg", &res); if (ret) return ret;
Applied. M
