Implement board_debug_uart_init() for Trogdor boards so that the debug
UART can be used. Initialize the clk to XO speed (19.2MHz) and change
the pin configuration to mux out the uart hardware on the pins that are
connected to the closed case debug (CCD) port for the AP. This is enough
to get the early debug console working on boards like Lazor, but it
should work for all Google Trogdor boards.
Signed-off-by: Stephen Boyd <swb...@chromium.org>
---
board/google/trogdor/Makefile | 3 +++
board/google/trogdor/debug.config | 6 +++++
board/google/trogdor/debug_uart.c | 41 +++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+)
create mode 100644 board/google/trogdor/Makefile
create mode 100644 board/google/trogdor/debug.config
create mode 100644 board/google/trogdor/debug_uart.c
diff --git a/board/google/trogdor/Makefile b/board/google/trogdor/Makefile
new file mode 100644
index 000000000000..fd2933cf1e6f
--- /dev/null
+++ b/board/google/trogdor/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += debug_uart.o
diff --git a/board/google/trogdor/debug.config
b/board/google/trogdor/debug.config
new file mode 100644
index 000000000000..7d8a6706a92e
--- /dev/null
+++ b/board/google/trogdor/debug.config
@@ -0,0 +1,6 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_BASE=0xa88000
+CONFIG_DEBUG_UART_MSM_GENI=y
+CONFIG_DEBUG_UART_CLOCK=36864000
+CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/board/google/trogdor/debug_uart.c
b/board/google/trogdor/debug_uart.c
new file mode 100644
index 000000000000..3d15d0d77728
--- /dev/null
+++ b/board/google/trogdor/debug_uart.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/io.h>
+#include <debug_uart.h>
+#include <linux/delay.h>
+
+/*
+ * Enable the UART8 clks and pinctrl settings for SC7180.
+ *
+ * The debug UART goes out over CCD. The debug uart clk setting is 36864000 to
+ * make the buad rate calculation come out properly for the qcom geni serial
+ * driver.
+ */
+void board_debug_uart_init(void)
+{
+ u32 val, mask;
+ unsigned int timeout = 100;
+
+ /* Enable wrap1_s2 clk */
+ val = readl(0x100000 + 0x52008);
+ val |= BIT(24);
+ writel(val, 0x100000 + 0x52008);
+ /* Wait for enable */
+ do {
+ val = readl(0x100000 + 0x18274);
+ mask = GENMASK(30, 28) | BIT(31);
+ val &= mask;
+ if ((val & BIT(31)) == 0 || ((val >> 28) & 7) == 1)
+ break;
+ udelay(10);
+ } while (timeout--);
+
+ /*
+ * Configure GPIOs
+ * Bits: 0-1 = pull
+ * Bits: 2-4 = func
+ * Bits: 6-8 = drive strength
+ */
+ writel(0x3 | (1 << 2), 0x3900000 + (0x1000 * 44)); // Pin 44 - PULL_UP,
func1 (qup12), 2ma
+ writel(0x3 | (1 << 2), 0x3900000 + (0x1000 * 45)); // Pin 45 - PULL_UP,
func1 (qup12), 2ma
+}
--
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