On 5/22/25 09:08, Gabriel FERNANDEZ wrote: > > On 5/21/25 15:41, Patrice Chotard wrote: >> From: Gabriel Fernandez <gabriel.fernan...@foss.st.com> >> >> Add clock driver support for STM32MP25 SoCs. >> >> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@foss.st.com> >> Signed-off-by: Valentin Caron <valentin.ca...@foss.st.com> >> Signed-off-by: Patrice Chotard <patrice.chot...@foss.st.com> >> Cc: Lukasz Majewski <lu...@denx.de> >> Cc: Sean Anderson <sean...@gmail.com> >> --- [...] >> + GATE_UART7, >> + GATE_UART8, >> + GATE_UART9, >> + GATE_USART1, >> + GATE_USART2, >> + GATE_USART3, >> + GATE_USART6, >> + GATE_USB2, > please rename GATE_USB2 into GATE_USBH to be conform with last reference > manual Ok >> + GATE_USB2PHY1, >> + GATE_USB2PHY2, >> + GATE_USB3DR, >> + GATE_USB3PCIEPHY, >> + GATE_USBTC, >> + GATE_VDEC, >> + GATE_VENC, >> + GATE_VREF, >> + GATE_WWDG1, >> + GATE_WWDG2, [...] >> + GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), >> + GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), >> + GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), >> + GATE_CFG(GATE_USB2, RCC_USB2CFGR, 1, 0), > > GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0), Ok > >> + GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), >> + GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), >> + GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), >> + GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), >> + GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0), [...] >> + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY1, "ck_ker_usb2phy1", 0, >> + SECF_NONE, GATE_USB2PHY1, MUX_USB2PHY1), >> + >> + /* USBH */ >> + STM32_GATE(CK_BUS_USB2OHCI, "ck_icn_m_usb2ohci", "ck_icn_hsl", 0, >> GATE_USB2, SECF_NONE), >> + STM32_GATE(CK_BUS_USB2EHCI, "ck_icn_m_usb2ehci", "ck_icn_hsl", 0, >> GATE_USB2, SECF_NONE), > > STM32_GATE(CK_BUS_USB2OHCI, "ck_icn_m_usb2ohci", "ck_icn_hsl", 0, GATE_USBH, > SECF_NONE), > STM32_GATE(CK_BUS_USB2EHCI, "ck_icn_m_usb2ehci", "ck_icn_hsl", 0, GATE_USBH, > SECF_NONE), > >> + >> + /* USB2PHY2 */ >> + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY2EN, "ck_ker_usb2phy2_en", 0, >> + SECF_NONE, GATE_USB2PHY2, MUX_USB2PHY2), >> + >> + /* USB3 PCIe COMBOPHY */ [...] >> +#define RCC_ADC12CFGR 0x7E8 >> +#define RCC_ADC3CFGR 0x7EC >> +#define RCC_ETH1CFGR 0x7F0 >> +#define RCC_ETH2CFGR 0x7F4 >> +#define RCC_USB2CFGR 0x7FC > > #define RCC_USBHCFGR Ok > > Best regards, > > Gabriel > >> +#define RCC_USB2PHY1CFGR 0x800 >> +#define RCC_USB2PHY2CFGR 0x804 >> +#define RCC_USB3DRCFGR 0x808 >> +#define RCC_USB3PCIEPHYCFGR 0x80C >> +#define RCC_PCIECFGR 0x810
