TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.
Signed-off-by: Yao Zi <zi...@disroot.org>
---
arch/riscv/cpu/th1520/dram.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c
index 91007c0a3d3..8a0ca26785e 100644
--- a/arch/riscv/cpu/th1520/dram.c
+++ b/arch/riscv/cpu/th1520/dram.c
@@ -19,3 +19,19 @@ int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+
+ return gd->ram_top;
+}
--
2.50.0
