Hi > -----Original Message----- > From: Peng Fan <peng....@oss.nxp.com> > Sent: Friday, 11 July 2025 11:54 am > To: Maniyam, Dinesh <dinesh.mani...@altera.com> > Cc: u-boot@lists.denx.de; Marek <ma...@denx.de>; Simon > <simon.k.r.goldschm...@gmail.com>; Simon Glass <s...@chromium.org>; Tom > Rini <tr...@konsulko.com>; Chee, Tien Fong <tien.fong.c...@altera.com>; > Hea, Kok Kiang <kok.kiang....@altera.com>; Ng, Boon Khai > <boon.khai...@altera.com>; Yuslaimi, Alif Zakuan > <alif.zakuan.yusla...@altera.com>; Lim, Jit Loon <jit.loon....@altera.com>; > Dinesh Maniyam <dinesh.mani...@intel.com> > Subject: Re: [PATCH] configs: Relocate malloc and bss address > > [CAUTION: This email is from outside your organization. Unless you trust the > sender, do not click on links or open attachments as it may be a fraudulent > email attempting to steal your information and/or compromise your > computer.] > > On Thu, Jul 10, 2025 at 12:12:53PM +0800, dinesh.mani...@altera.com > wrote: > >From: Dinesh Maniyam <dinesh.mani...@intel.com> > > > > Nit, update subject with socfpga_agilex5: config: >
Noted. I will update it. > >With Inline ECC enabled, the bottom 1/8 of DDR is reserved for ECC > >parity bits and must not be used for general data address allocation. > >Previously, the SPL bss and malloc addresses were allocated inside this > >ECC parity region if the DDR size is 1GB. > > > >This caused ECC hardware to detect stale or invalid parity bits, > >leading to data correction attempts and DMA polling hangs or failures. > > > >Fix this by relocating the malloc and bss to the usable 7/8 region of > >DDR and is fully ECC-safe. > > > >This change ensures reliable ddr address operation and prevents > >unintended memory corruption. > > > >Signed-off-by: Dinesh Maniyam <dinesh.mani...@intel.com> > >--- > > configs/socfpga_agilex5_defconfig | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > >diff --git a/configs/socfpga_agilex5_defconfig > >b/configs/socfpga_agilex5_defconfig > >index 4ac0a5d9b99..01c5ac88015 100644 > >--- a/configs/socfpga_agilex5_defconfig > >+++ b/configs/socfpga_agilex5_defconfig > >@@ -12,7 +12,7 @@ > CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk" > > CONFIG_DM_RESET=y > > CONFIG_SPL_STACK=0x7d000 > > CONFIG_SPL_HAS_BSS_LINKER_SECTION=y > >-CONFIG_SPL_BSS_START_ADDR=0xbff00000 > >+CONFIG_SPL_BSS_START_ADDR=0x9ff00000 > > Commit says bottom is reserved, but here bss start is moved to low address. > ECC area is at top area? > > Regards, > Peng The idea here is to move the bss_start_addr to DDR base address + 512MB. The ECC-reserved area remains at the lower end of DDR, and since Agilex 5 requires a minimum DDR size of 1GB, this memory layout is safe. This approach maintains consistency with the existing memory layout logic defined for previous SoCs in: include/configs/socfpga_soc64_common.h Regards Dinesh
