[PATCH] airoha: rework RAM size handling to support multiple RAM size

[Christian Marangi]

There are multiple version of the same reference board with different
RAM size and it's not enough to base the RAM size entirely from DT. To
better support it use the get_ram_size way to scan for the actual RAM
size of Airoha SoC and increase the size of the memory map.

Signed-off-by: Christian Marangi <ansuels...@gmail.com>
---
 arch/arm/mach-airoha/an7581/init.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-airoha/an7581/init.c 
b/arch/arm/mach-airoha/an7581/init.c
index d149e0ee3c8..0f72365c4ab 100644
--- a/arch/arm/mach-airoha/an7581/init.c
+++ b/arch/arm/mach-airoha/an7581/init.c
@@ -2,10 +2,14 @@
 
 #include <fdtdec.h>
 #include <init.h>
+#include <linux/sizes.h>
 #include <sysreset.h>
 #include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
 #include <asm/system.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int print_cpuinfo(void)
 {
        printf("CPU:   Airoha AN7581\n");
@@ -14,12 +18,23 @@ int print_cpuinfo(void)
 
 int dram_init(void)
 {
-       return fdtdec_setup_mem_size_base();
+       int ret;
+
+       ret = fdtdec_setup_mem_size_base();
+       if (ret)
+               return ret;
+
+       gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G);
+
+       return 0;
 }
 
 int dram_init_banksize(void)
 {
-       return fdtdec_setup_memory_banksize();
+       gd->bd->bi_dram[0].start = gd->ram_base;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+
+       return 0;
 }
 
 void reset_cpu(void)
@@ -32,12 +47,12 @@ static struct mm_region an7581_mem_map[] = {
                /* DDR */
                .virt = 0x80000000UL,
                .phys = 0x80000000UL,
-               .size = 0x80000000UL,
+               .size = 0x200000000ULL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
        }, {
                .virt = 0x00000000UL,
                .phys = 0x00000000UL,
-               .size = 0x20000000UL,
+               .size = 0x40000000UL,
                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
                         PTE_BLOCK_NON_SHARE |
                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
-- 
2.50.0