GB200 is an Aspeed 2600 based BMC+baseboard for NVIDIA's Blackwell GB200
platform.
UT3.0b is a unit tester variant that uses a different networking topology.

Reference to Ast2600 SOC [1].
Reference to Blackwell GB200NVL Platform [2].

Link: https://www.aspeedtech.com/server_ast2600/ [1]
Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2]

Signed-off-by: Donald Shannon <dona...@nvidia.com>
---
 arch/arm/dts/Makefile                       |   1 +
 arch/arm/dts/ast2600-gb200-ut30b-nvidia.dts | 238 ++++++++++++++++++++
 2 files changed, 239 insertions(+)
 create mode 100644 arch/arm/dts/ast2600-gb200-ut30b-nvidia.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dbb2fafc4f..92a529e8f5 100755
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -688,6 +688,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
        ast2600-evb.dtb \
        ast2600-facebook.dtb \
        ast2600-fpga.dtb \
+       ast2600-gb200-ut30b-nvidia.dtb \
        ast2600-gb200nvl-bmc-nvidia.dtb \
        ast2600-greatlakes.dtb \
        ast2600-intel.dtb \
diff --git a/arch/arm/dts/ast2600-gb200-ut30b-nvidia.dts 
b/arch/arm/dts/ast2600-gb200-ut30b-nvidia.dts
new file mode 100644
index 0000000000..68e1f51fe7
--- /dev/null
+++ b/arch/arm/dts/ast2600-gb200-ut30b-nvidia.dts
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "ast2600-u-boot.dtsi"
+
+/ {
+       model = "AST2600 GB200 UT3.0b BMC";
+       compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600";
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x40000000>;
+       };
+
+       chosen {
+               stdout-path = &uart5;
+       };
+
+       aliases {
+               mmc0 = &emmc_slot0;
+               mmc1 = &sdhci_slot0;
+               mmc2 = &sdhci_slot1;
+               spi0 = &fmc;
+               spi1 = &spi1;
+               spi2 = &spi2;
+               ethernet0 = &mac0;
+               ethernet1 = &mac1;
+               ethernet2 = &mac2;
+               ethernet3 = &mac3;
+       };
+
+       cpus {
+               cpu@0 {
+                       clock-frequency = <800000000>;
+               };
+               cpu@1 {
+                       clock-frequency = <800000000>;
+               };
+       };
+};
+
+&uart5 {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&sdrammc {
+       clock-frequency = <400000000>;
+};
+
+&wdt1 {
+       status = "okay";
+};
+
+&wdt2 {
+       status = "okay";
+};
+
+&wdt3 {
+       status = "okay";
+};
+
+&mdio {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_mdio1_default>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       ethphy0: ethernet-phy@0 {
+               reg = <0>;
+       };
+};
+
+&mac0 {
+       status = "okay";
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&ethphy0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+&fmc {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_fmcquad_default>;
+
+       flash@0 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "okay";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+
+       flash@1 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "okay";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+
+       flash@2 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "okay";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
+&spi1 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
+                       &pinctrl_spi1cs1_default &pinctrl_spi1wp_default
+                       &pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
+
+       flash@0 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "okay";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+
+       flash@1 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "disabled";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+};
+
+&spi2 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
+                       &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
+       num-cs = <1>;
+
+       flash@0 {
+               compatible = "spi-flash", "sst,w25q256";
+               status = "okay";
+               spi-max-frequency = <50000000>;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+       };
+
+};
+
+&i2c4 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c5_default>;
+};
+
+&i2c5 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c6_default>;
+};
+
+&i2c6 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c7_default>;
+};
+
+&i2c7 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c8_default>;
+};
+
+&i2c8 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c9_default>;
+};
+
+&i2c10 {
+       status = "okay";
+
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c11_default>;
+};
+
+&pcie_phy1 {
+       status = "okay";
+};
+
+&pcie_bridge {
+       status = "okay";
+};
+
+&ehci1 {
+       status = "okay";
+};
+
+&scu {
+       mac0-clk-delay = <0x10 0x0a
+                         0x10 0x10
+                         0x10 0x10>;
+       mac1-clk-delay = <0x10 0x0a
+                         0x10 0x10
+                         0x10 0x10>;
+       mac2-clk-delay = <0x08 0x04
+                         0x08 0x04
+                         0x08 0x04>;
+       mac3-clk-delay = <0x08 0x04
+                         0x08 0x04
+                         0x08 0x04>;
+};
+
+&hace {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&acry {
+       u-boot,dm-pre-reloc;
+       status = "okay";
+};
+
+&display_port {
+       status = "okay";
+};
-- 
2.43.0

Reply via email to